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FN7173.3

November 12, 2010

The signal is processed through an active 3 pole filter (F1)

designed for minimum ripple with constant phase delay. The

filter attenuates the color burst by 12dB and eliminates fast

transient spikes without sync crushing. An external filter is

not necessary. The filter also amplifies the video signal by

6dB to improve the detection accuracy. The filter cut-off

frequency is controlled by an external resistor from pin 1 to

ground.

to supply voltage variation are derived on the chip.

voltage of 1.7V nominal. Consequently, it can be seen that

about 6k

excellent supply voltage rejection.

To improve noise immunity, the output of the 3 pole filter is

brought out to pin 7. It is recommended to AC couple the

output to pin 8, the video input pin. In case of strong clean

video signal, the video input pin, pin 8, can be driven by the

signal directly.

Comparator C2 on the input to the sample and hold block

(S/H) compares the leading and trailing edges of the sync.

initiates the timing one-shots for gating the sample and hold

circuits. The sample of the sync tip is delayed by 0.8µs to

enable the actual sample of 2µs to be taken on the optimum

section of the sync. pulse tip. The acquisition time of the

circuit is about three horizontal lines. The double poly CMOS

technology enables long time constants to be achieved with

small high quality on-chip capacitors. The back porch

voltage is similarly derived from the trailing edge of sync,

which also serves to cut off the tip sample if the gate time

exceeds the tip period. Note that the sample and hold gating

The 50% level of the sync tip is derived through the resistor

This comparator has built in hysteresis to avoid false

triggering. The output of C2 is a digital 5V signal which feeds

the C/S output buffer B1, the vertical, back porch and

odd/even functions.

The vertical circuit senses C/S edges and initiates an

integrator which is reset by the shorter horizontal sync

pulses but times out with the longer vertical sync. pulse

timing current. The vertical output pulse is started on the first

serration pulse in the vertical interval and is then self-timed

out. In the absence of a serration pulse, an internal timer will

default the start of vertical.

The horizontal circuit senses C/S edges and produces the

true horizontal pulses of nominal width 5µs. The leading

edge is triggered from the leading edge of the input H sync,

with the same prop. delay as composite sync. The half line

pulses present in the input signal during vertical blanking are

removed with an internal 2H eliminator circuit. The 2H

eliminator initiates a time out period after a horizontal pulse

The back porch is triggered from the sync tip trailing edge

and initiates a one-shot pulse. The period of this pulse is

set by RESET.

The odd/even circuit (O/E) tracks the relationship of the

horizontal pulses to the leading edge of the vertical output

and will switch on every field at the start of vertical. Pin 13 is

high during an odd field.

Loss of video signal can be detected by monitoring the No

Signal Detect Output pin 10. The VTIP voltage held by the

on pin 2. Pin 10 output goes high when the VTIP falls below

VTIP voltage is also passed through an amplifier with gain of

2 and buffed to pin 9. This provides an indication of signal

strength. This signal (Level Output) can be used for AGC

applications.

EL4583