8

FN7441.5

September 22, 2009

Signals A and B are derived from the video input by

comparing the video signal with a slicing level, which is set by

an internal DAC. This enables the delay to be measured

either from the rising edges of sync-like signals encoded on

top of the video or from a dedicated set-up signal. The outputs

can be used to set the correct delays for the signals received.

The DAC level is set through the serial input by bits 1

through 4 directed to the test register (00).

Test Mode

Bit zero of the test register is set to 0 for normal operation. If

it is set to 1 then the device is in Test Mode. In Test Mode,

the DAC voltage is directed to the Green channel output,

while for the Red and Blue channels, the test outputs are

now pulses of current which are generated by looking at the

delay between the input and output of the channel. They

thus enable the delay to be measured.

FIGURE 15. DELAY DETECTOR

A

B

OUTPUT

4

SLICING LEVEL

COMPARATORS

A

B

VIDEO IN

TABLE 2.

wxyz

DAC/mV

1000

-400

1001

-350

1010

-300

1011

-250

1100

-200

1101

-150

1110

-100

1111

-50

0000

0

0001

50

0010

100

0011

150

0100

200

0101

250

0110

300

0111

350

NOTE: Test Register word = 000wxyzt. If t = 1 test mode else

normal. wxyz fed to DAC. z is LSB

EL9115