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CY8C28545-24AXIT Datasheet(PDF) 3 Page - Cypress Semiconductor |
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CY8C28545-24AXIT Datasheet(HTML) 3 Page - Cypress Semiconductor |
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3 / 78 page  CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Document Number: 001-48111 Rev. *I Page 3 of 78 PSoC Functional Overview The PSoC family consists of many devices with On-Chip Controllers. These devices are designed to replace multiple traditional MCU based system components with one low cost single chip programmable component. A PSoC device includes configurable analog blocks, digital blocks, and interconnections. This architecture enables the user to create customized peripheral configurations to match the requirements of each individual application. In addition, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages. The CY8C28xxx group of PSoC devices described in this datasheet have multiple resource configuration options available. Therefore, not every resource mentioned in this datasheet is available for each CY8C28xxx subgroup. The CY8C28x45 subgroup has a full feature set of all resources described. There are six more segmented subgroups that allow designers to use a device with only the resources and function- ality necessary for a specific application. See Table 2 on page 8 to determine the resources available for each CY8C28xxx subgroup. The same information is also presented in more detail in the Ordering Information section. The architecture for this specific PSoC device family, as shown in the Logic Block Diagram on page 1, consists of four main areas: PSoC Core, Digital System, Analog System, and System Resources. The configurable global bus system allows all the device resources to be combined into a complete custom system. PSoC CY8C28xxx family devices have up to six I/O ports that connect to the global digital and analog interconnects, providing access to up to 12 digital blocks and up to 16 analog blocks. The PSoC Core The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable general Purpose I/O (GPIO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microcontroller. Memory encompasses 16K bytes of Flash for program storage, 1K bytes of SRAM for data storage. The PSoC device incorpo- rates flexible internal clock generators, including a 24 MHz internal main oscillator (IMO) accurate to 2.5% over temperature and voltage. A low power 32 kHz internal low speed oscillator (ILO) is provided for the sleep timer and watch dog timer (WDT). The 32.768 kHz external crystal oscillator (ECO) is available for use as a real time clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. PSoC GPIOs provide connections to the CPU, and digital and analog resources. Each pin’s drive mode may be selected from 8 options, which allows great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. The Digital System The Digital System is composed of up to 12 configurable digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to create 8, 16, 24, and 32-bit peripherals, which are called user modules. The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. Figure 1. Digital System Block Diagram[1] Digital peripheral configurations include: ■ PWMs (8 to 16 bit, One-shot and Multi-shot capability) ■ PWMs with Dead band/Kill (8 to 16 bit) ■ Counters (8 to 32 bit) ■ Timers (8 to 32 bit) ■ Full-duplex 8-bit UARTs (up to 3) with selectable parity ■ Half-duplex 8-bit UARTs (up to 6) with selectable parity ■ Variable length SPI slave and master ❐ Up to 6 total slaves and masters (8-bit) ❐ Supports 8 to 16 bit operation ■ I 2C slave, master, or multi-master (up to 2 available as System Resources) ■ IrDA (up to 3) ■ Pseudo Random Sequence Generators (8 to 32 bit) ■ Cyclical Redundancy Checker/Generator (16 bit) ■ Shift Register (2 to 32 bit) DIGITAL SYSTEM To System Bus Digital Clocks From Core Digital PSoC Block Array To Analog System 8 8 8 8 GIE[7:0] GIO[7:0] Global Digital Interconnect Port 4 Port 3 Port 2 Port 1 Port 0 Port 5 GOO[7:0] GOE[7:0] Row 0 DBC00 DBC01 DCC02 DCC03 4 4 Row 1 DBC10 DBC11 DCC12 DCC13 4 4 Row 2 DBC20 DBC21 DCC22 DCC23 4 4 Note 1. CY8C28x52 devices do not have digital block row 2. They have two digital rows with eight total digital blocks. |
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