For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824

978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com

Application Support: apps@hittite.com

0

0 - 10

HMCAD1051-40

v01.0411

Single 13/12-Bit 20/40 MSPS

A/D Converter

Figure 8: Alternative input network

Clock Input and Jitter considerations

typically high-speed ADCs use both clock edges to

generate internal timing signals. In the HMCAD1051-

40 only the rising edge of the clock is used. Hence,

input clock duty cycles between 20% and 80% are

acceptable.

the input clock can be supplied in a variety of formats.

the clock pins are AC-coupled internally. Hence a

wide common mode voltage range is accepted. Differ-

ential clock sources as LvDs, LvPeCL or differential

sine wave can be connected directly to the input pins.

For CMos inputs, the CKn pin should be connected

to ground, and the CMos clock signal should be con-

nected to CKP. For differential sine wave clock, the

input amplitude must be at least ± 800 mvpp.

the quality of the input clock is extremely important

for high-speed, high-resolution ADCs. the contribu-

tion to snr from clock jitter with a full scale signal at a

given frequency is shown in equation 1,

SNR

(1)

where fIn is the signal frequency, and

εt is the total

rms jitter measured in seconds. the rms jitter is the

total of all jitter sources including the clock generation

circuitry, clock distribution and internal ADC circuitry.

For applications where jitter may limit the obtainable

performance, it is of utmost importance to limit the

clock jitter. this can be obtained by using precise and

stable clock references (e.g. crystal oscillators with

good jitter specifications) and make sure the clock dis-

tribution is well controlled. It might be advantageous

to use analog power and ground planes to ensure

low noise on the supplies to all circuitry in the clock

distribution. It is of utmost importance to avoid cross-

talk between the ADC output bits and the clock and

between the analog input signal and the clock since

such crosstalk often results in harmonic distortion.

the jitter performance is improved with reduced rise

and fall times of the input clock. Hence, optimum jitter

performance is obtained with LvDs or LvPeCL clock

with fast edges. CMos and sine wave clock inputs will

result in slightly degraded jitter performance.

If the clock is generated by other circuitry, it should

be re-timed with a low jitter master clock as the last

operation before it is applied to the ADC clock input.

Digital Outputs

Digital output data are presented on parallel CMos

form. the voltage on the ovDD pin set the levels of the

CMos outputs. the output drivers are dimensioned to

drive a wide range of loads for ovDD above 2.25v,

but it is recommended to minimize the load to ensure

as low transient switching currents and resulting noise

as possible. In applications with a large fanout or large

capacitive loads, it is recommended to add external

buffers located close to the ADC chip.

the timing is described in the timing Diagram section.

note that the load or equivalent delay on CK_eXt

always should be lower than the load on data outputs

to ensure sufficient timing margins.

the digital outputs can be set in tristate mode by set-

ting the oe_n signal high.

the HMCAD1051-40 employs digital offset correc-

tion. this means that the output code will be 4096 with

shorted inputs. However, small mismatches in para-

sitics at the input can cause this to alter slightly. the

offset correction also results in possible loss of codes

at the edges of the full scale range. With no offset

correction, the ADC would clip in one end before the

other, in practice resulting in code loss at the oppo-

site end. With the output being centered digitally, the

output will clip, and the out of range flags will be set,

before max code is reached. When out of range flags

are set, the code is forced to all ones for over range

and all zeros for under range.

note that the out of range flags (ornG) will behave

differently for 12 bit and 13 bit output. For 13 bit output

ornG will be set when digital output data are all ones

or all zeros. For 12-bit output the ornG flags will be

set when all twelve bits are zeros or ones and when

the thirteenth bit is equal to the rest of the bits.

Data Format Selection

the output data are presented on offset binary form

when DFrMt is low (connect to ovss). setting

DFrMt high (connect to ovDD) results in 2’s comple-

ment output format. Details are shown in table 3.