DS31408

3

Typical Line Card Application Example, Traditional Frequency Synchronization

DPLL1 Path

system timing

from master and slave

timing cards

IC1

DS31408

DPLL2 Path

IC2

19.44MHz, 38.88MHz,

25MHz, etc.

line timing

to master and slave

timing cards

8kHz, 19.44MHz,

38.88MHz, 25MHz, etc.

OC6

OC7

n

recovered line clocks from SERDES

SONET/SDH, 1GE, 10GE, OTN, FC etc.

frequencies can be unrelated to one another

155.52M, 622.08M, 25M,

125M, 156.25M, etc. with or

without fractional scaling for

FEC, 64B/66B, etc.

MANY other rates possible,

including DS1, E1, DS3, E3,

10M and Nx19.44M.

IC3 to IC8

n

3 unrelated frequencies simultaneously with <1ps rms jitter

plus other frequencies with somewhat higher jitter

clock monitoring and selection,

undo fractional scaling,

frequency conversion

clock monitoring and selection,

hitless switching, holdover, frequency

conversion, fractional scaling,

jitter attenuation

OC1 to OC5

clocks to line card SERDES

SONET/SDH, 1GE, 10GE, OTN, FC, etc.

Typical Application Example, Frequency and Time Synchronization

system time, e.g. 1 PPS

to all port cards

line clocks, e.g. 25MHz

from port cards,

for SyncE or

1588+SyncE operation

DS31408

SPI

Local OSC

TCXO or

OCXO

system clock, e.g. 25MHz

other clocks

Processor

1588

Software

packet data to/from central switch function

DPLL

1588

Clock

ABRIDGED DATA SHEET