ISL9492

2

FN6547.1

March 17, 2011

Pin Configuration

ISL9492

(28 LD TQFN)

TOP VIEW

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

PART

MARKING

TEMP.

RANGE (°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

ISL9492ERZ

94 92ERZ

-20 to +85

28 Ld 4x4 TQFN

L28.4x4A

ISL9492QFNEVAL1

Evaluation Board

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-

free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL9492. For more information on MSL please see techbrief TB363.

1

2

3

4

5

6

7

8

910

11

12

13

20

19

18

17

16

15

21

CPSWIN

VSWSNS

NC

NC

ABYP

VCC

DRAIN

FLT

LDO_SGND

EXTM

TXT

SCL

SDA

TDOUT

28

27

26

25

24

23

14

22

Functional Pin Descriptions

PIN

SYMBOL

FUNCTION

1

CPSWIN

Charge pump connection 1

2

VSWSNS

Boost regulator sense line. Connect to boost output capacitor.

3, 4

NC

No connect pins

5

ABYP

Analog 5V supply. Decouple with 1µF ceramic capacitor and a ferrite bead (see “ABYP” on page 14 for

more detail).

6

VCC

Main power supply to the chip.

7

DRAIN

This is the Drain of the Boost MOSFET. The Boost inductor will be connected to this pin.

8,9

PGND

Power gound for the Internal Boost MOSFET.

10

DBYP

Digital 5V supply. Decouple with 1µF ceramic capacitor.

11, 12

ADDR0, ADDR1

Logic combination at the ADD0 and ADD1 can select four different chip select addresses.

13

SVTOP

External control of output voltage selection.

14

TDIN

Tone detector input.

15

TDOUT

The envelope of the actually detected external tone signal. It is an open-drain output.