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X9421YV14 Datasheet(PDF) 1 Page - Intersil Corporation |
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X9421YV14 Datasheet(HTML) 1 Page - Intersil Corporation |
1 / 20 page 1 ® FN8196.4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9421 Low Noise/Low Power/SPI Bus Single Digitally Controlled (XDCP™) Potentiometer Description The X9421 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Power-up recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Features • Single Voltage Potentiometer • 64 Resistor Taps • SPI Serial Interface for Write, Read, and Transfer Operations of the Potentiometer • Wiper Resistance, 150 Ω Typical at 5V • 4 Non-Volatile Data Registers • Non-Volatile Storage of Multiple Wiper Positions • Power-on Recall. Loads Saved Wiper Position on Power-up. • Standby Current < 5µA Max •VCC : 2.7V to 5.5V Operation •2.5k Ω, 10kΩ End to End Resistance • 100 yr. Data Retention • Endurance: 100, 000 Data Changes per Bit per Register • 14 Ld TSSOP, 16 Ld SOIC • Low Power CMOS • Pb-Free Available (RoHS Compliant) Block Diagram 64-TAPS 10k Ω INC / DEC RH/VH RL/VL RW/VW POT VCC VSS SPI BUS ADDRESS DATA STATUS WRITE READ WIPER TRANSFER POWER-ON RECALL WIPER COUNTER REGISTER (WCR) DATA REGISTERS 4 BYTES CONTROL INTERFACE BUS INTERFACE & CONTROL Data Sheet January 14, 2009 NOT REC OMM END ED F OR NEW DES IGN S POS SIBL E SU BST ITUT E PR ODU CT ISL2 2416 , ISL 2241 9 |
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