BD8105FV

Technical Note

11/12

www.rohm.com

2011.05 - Rev.C

© 2011 ROHM Co., Ltd. All rights reserved.

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Notes for use

(1) Absolute maximum ratings

Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may

result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such

damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special

mode where the absolute maximum ratings may be exceeded is anticipated.

(2) Reverse connection of a power supply connector

If the connector of power is wrong connected, it may result in IC breakage. In order to prevent the breakage from the

wrong connection, the diode should be connected between external power and the power terminal of IC as protection

solution.

(3) GND potential

Ensure a minimum GND pin potential in all operating conditions.

(4) Setting of heat

Use a setting of heat that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.

(5) Pin short and mistake fitting

Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in

damage to the IC. Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating

temperature range may result in IC damage.

(6) Actions in strong magnetic field

Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to

malfunction.

(7) Thermal shutdown circuit(TSD)

This IC built-in a Thermal shutdown circuit (TSD circuit). If Chip temperature becomes 175℃(TYP.), make the output an

Open state. Eventually, warmly clearing the circuit is decided by the condition of whether the heat excesses over the

assigned limit, resulting the cutoff of the circuit of IC, and not by the purpose of preventing and ensuring the IC. Therefore,

the warm switch-off should not be applied in the premise of continuous employing and operation after the circuit is

switched on.

(8) Testing on application boards

When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.

Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure,

and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or

removing it from a jig or fixture during the inspection process

(9) IC terminal input

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.

P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of

parasitic elements. For example, when a resistor and transistor are connected to pins. (See the chart below.)



the P/N junction functions as a parasitic diode when

GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN).



Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer

of other adjacent elements to operate as a parasitic NPN transistor.

The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result

of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC

malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will

trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (PCB) voltage to

input pins.

(10) Ground wiring patterns

When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,

placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage

variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the

GND wiring patterns of any external components.

(Pin A)

GND

N

P

N

N

P+

P+

Resistor

Parasitic elements

P

Parasitic

elements

(Pin B)

GND

C

B

E

Parasitic

elements

GND

(Pin A)

GND

N

P

N

N

P+

P+

Parasitic elements

P substrate

(Pin B)

C

B

E

Transistor (NPN)

N

GND