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BD95513MUV Datasheet(PDF) 10 Page - Rohm

Part # BD95513MUV
Description  Switching Regulator with MOS FET for DDR-SDRAM Cores
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Manufacturer  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

BD95513MUV Datasheet(HTML) 10 Page - Rohm

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Technical Note
BD95513MUV
10/17
www.rohm.com
2010.10- Rev.A
© 2010 ROHM Co., Ltd. All rights reserved.
Operation
The BD95513MUV is a switching regulator incorporating ROHM’s proprietary H
3RegTM CONTROLLA control system.
When VOUT drops suddenly due to changes in load, the system quickly restores the output voltage by extending the ton time
interval. This improves the regulator’s transient response. When light-load mode is activated, the IC employs the Simple
Light Load Mode (SLLM
TM) controller, further improving system efficiency.
H
3RegTM Control
(Normal Operation)
(Rapid Changes in Load)
Light Load Control
(SLLM
TM Mode)
(QLLM Mode)
VFB
VREF
HG
LG
High gate output is determined by the above formula.
When VFB falls below the reference voltage (0.7V),
the H
3RegTM CONTROLLA is activated;
VFB
VREF
HG
Io
LG
tON
When VOUT drops due to a sudden change in load and the
voltage remains below VREF after the preprogrammed tON time
interval has elapsed, the system quickly restores VOUT by
extending the tON time, thereby improving transient response.
tON =
VREF
VIN
×
1
f
[sec]・・・(1)
SLLM
TM mode is enabled by setting the MODE pin to logic high.
When the low gate is off and the current through the inductor is 0
(current flowing from VOUT to SW), the SLLM
TM function is
activated, disabling high gate output.
If VFB falls below VREF again, the high gate is switched back on,
lowering the switching frequency of the regulator and yielding
higher efficiency when powering light loads.
VFB
VREF
HG
LG
0A
QLLM mode is enabled by setting the MODE pin to HiZ or
middle voltage. When the lower gate is off and the current
through the inductor is 0 (current flowing from VOUT to SW),
QLLM mode is activated, disabling high gate output.
If VFB falls below VREF within a programmed time interval
(typ. 40 µs), the high gate is switched on, but if VFB does not fall
below VREF, the lower gate is forced on, dropping VFB and
switching the high gate back on.
The minimum switching frequency is set to 25 kHz (T = 40 µs),
which keeps the regulator’s frequency from entering the audible
spectrum but yields less efficient results than SLLM
TM mode.
VFB
VREF
HG
LG
0A


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