BU90R104-E2 datasheet(5/18 Pages) ROHM

Part #	BU90R104-E2

Description	35bit LVDS Receiver 5:35 DeSerializer

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Manufacturer	ROHM [Rohm]

Direct Link	http://www.rohm.com

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Technical Note

5/17

www.rohm.com

2011.02 - Rev.A

BU90R104

●

Pin Description

Pin Name

Pin No.

I/O

Description

RA+, RA-

50,49

LVDS Input

LVDS data input

+ : Positive input of LVDS data differential pair.

- : Negative input of LVDS data differential pair.

RB+, RB-

52,51

LVDS Input

RC+, RC-

55,54

LVDS Input

RD+, RD-

60,59

LVDS Input

RE+, RE-

62,61

LVDS Input

RCLK+, RCLK-

57,56

LVDS Input

LVDS clock input

RA6～RA0

40,41,42,43,

45,46,47

Output

LVCMOS data outputs.

RB6～RB0

32,33,34,35,

36,38,39

Output

RC6～RC0

22,24,25,26,

27,28,29

Output

RD6～RD0

14,15,17,18,

19,20,21

Output

RE6～RE0

6,7,8,10,

11,12,13

Output

RESERVE

2

Input

Reserved input must be “Low” for normal operation.

PD

3

Input

Power down input for the internal system.

H : Normal operation.

L : Power down (All output are “Low”).

OE

4

Input

Power down input for the data output driver.

H : Output enable (Normal operation).

L : Output disable (All outputs are “Hi-Z”).

R/F

5

Input

Select input pin for data output clock triggering edge.

H : Output data is latched on rising edge.

L : Output data is latched on falling edge.

VDD

9,23,37,48

Power

3.3V output driver and digital core power supply pin.

CLKOUT

31

Output

LVCMOS level clock output.

GND

1,16,30,44

Ground

GND pin for both data output driver cells and the digital cores.

LVDD

53

Power

Power supply pin for LVDS inputs.

LGND

58

Ground

Ground pin for LVDS inputs.

PVDD

64

Power

Power supply pin for PLL core.

PGND

63

Ground

Ground pin for PLL core.

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