Technical Note

11/24

BU1852GUW

www.rohm.com

2011.01 - Rev.A

© 2011 ROHM Co., Ltd. All rights reserved.

3.

I

Each function of GPIO is controlled by internal registers. The I

registers. The device supports 400kHz Fast-mode data transfer rate.

Slave address

Two device addresses (Slave address) can be selected by ADR port.

A7

A6

A5

A4

A3

A2

A1

R/W

ADR=0

0

0

0

1

0

1

0

1/0

ADR=1

0

0

0

1

1

0

1

Data transfer

One bit of data is transferred during SCL = “1”. During the bit transfer SCL = “1” cycle, the signal SDA should keep

the value. If SDA changes during SCL = “1”, START condition or STOP condition occur and it is interpreted as a

control signal.

Fig.9 Data transfer

START・STOP・Repeated START conditions

When SDA and SCL are “1”, the data isn’t transferred on the I

to “0”, it means “Start condition” is occurred and access is started. If SCL remains “1” and SDA transfers from “0” to

“1”, it means “Stop condition” is occurred and access is stopped. It becomes repeated START condition (Sr) the

START condition enters again although the STOP condition is not done.

Fig.10 START・STOP・Repeated START conditions

SDA

SCL

Data is valid

when SDA is stable

SDA is

variable

SDA

SCL

S

Sr

START Condition

Repeated START Condition

P

STOP Condition