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BU99901GUZ-W Datasheet(PDF) 11 Page - Rohm

Part # BU99901GUZ-W
Description  WL-CSP EEPROM family I2C BUS
Download  17 Pages
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Manufacturer  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

BU99901GUZ-W Datasheet(HTML) 11 Page - Rohm

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Technical Note
11/16
BU99901GUZ-W
www.rohm.com
2010.09 - Rev.A
© 2010 ROHM Co., Ltd. All rights reserved.
Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kids of them are shown in the figure below. (Refer to Fig.41(a), Fig.41(b), Fig.41(c).) In dummy
clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level)
may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to
instantaneous power failure of system power source or influence upon devices.
Acknowledge polling
During internal write, all input commands are ignored, therefore ACK is not sent back. During internal automatic write
execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it
means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command
can be executed without waiting for tWR = 5ms.
When to write continuously,
W
/
R
= 0, when to carry out current read cycle after write, slave address
W
/
R
= 1 is sent,
and if ACK signal sends back 'L', then execute word address input and data so forth.
Fig.42 Case to continuously write by acknowledge polling
Slave
address
Word
address
S
T
A
R
T
First write command
A
C
K
H
A
C
K
L
Slave
address
Slave
address
Slave
address
Data
Write command
During internal write,
ACK = HIGH is sent back.
After completion of internal
write, ACK=LOW is sent back,
so input next word address and
data in succession.
tWR
tWR
Second write command
S
T
A
R
T
S
T
A
R
T
S
T
A
R
T
S
T
A
R
T
S
T
O
P
S
T
O
P
A
C
K
H
A
C
K
H
A
C
K
L
A
C
K
L
SCL
2
1
8
9
Dummy clock×9
Start
Fig.41-(b) The case of START+9 Dummy clock + START + command input
Start
Normal command
Normal command
SDA
1
2
13
14
SCL
Fig.41-(a) The case of 14 Dummy clock + START + START+ command input
Normal command
Normal command
Dummy clock×14
Start×2
* Start command from START input.
Start×9
Fig.41-(c) START × 9 + command input
SCL
1
2
3
8
9
7
SDA
SDA
Normal command
Normal command


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