4M (512K × 8) Flash Memory

LH28F004SU-Z1

7

COMMAND

FIRST BUS CYCLE

SECOND BUS CYCLE

NOTE

OPER.

ADDRESS

DATA

OPER.

ADDRESS

DATA

Read Array

Write

X

FFH

Read

AA

AD

Intelligent Identifier

Write

X

90H

Read

IA

ID

1

Read Compatible Status Register

Write

X

70H

Read

X

CSRD

2

Clear Status Register

Write

X

50H

3

Word Write

Write

X

40H

Write

WA

WD

Alternate Word Write

Write

X

10H

Write

WA

WD

Block Erase/Confirm

Write

X

20H

Write

BA

D0H

4

Erase Suspend/Resume

Write

X

B0H

Write

X

D0H

4

LH28F008SA-Compatible Mode Command Bus Definitions

ADDRESS

DATA

AA = Array Address

AD = Array Data

BA = Block Address

CSRD = CSR Data

IA = Identifier Address

ID = Identifier Data

WA = Write Address

WD = Write Data

X = Don’t Care

NOTES:

1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes.

2. The CSR is automatically available after device enters Data Write, Erase or Suspend operations.

3. Clears CSR.3, CSR.4, and CSR.5. See Status register definitions.

4. While device performs Block Erase, if you issue Erase Suspend command (B0H), be sure to confirm ESS (Erase-Suspend-Status) is

set to 1 on compatible status register. In the case, ESS bit was not set to 1, also completed the Erase (ESS = 0, WSMS = 1), be sure

to issue Resume command (D0H) after completed next Erase command. Beside, when the Erase Suspend command is issued, while

the device is not in Erase, be sure to issue Resume command (D0H) after the next erase complete.

LH28F004SU-Z1 Performance Enhancement Command Bus Definitions

ADDRESS

DATA

BA = Block Address

AD = Array Data

WA = Write Address

WD (L, H) = Write Data (Low, High)

X = Don’t Care

WD (H, L) = Write Data (High, Low)

NOTES:

1. After initial device power-up, or return from deep power-down mode, the block lock status bit default to the locked state independent of

the data in the corresponding lock bits. In order to upload the lock bit status, it requires to write Protect Set/Confirm command.

2. To reflect the actual lock-bit status, the Protect Set/Confirm command must be written after Lock Block/Confirm command.

3. When Protect Reset/Confirm command is written, all blocks can be written and erased regardless of the state of the lock-bits.

4. The Lock Block/Confirm command must be written after Protect Reset/Confirm command was written.

others are don’t care.

COMMAND

MODE

FIRST BUS CYCLE

SECOND BUS CYCLE

THIRD BUS CYCLE

NOTE

OPER. ADD.

DATA OPER.

ADD.

DATA

OPER.

ADD.

DATA

Protect Set/Confirm

Write

X

57H

Write

0FFH

D0H

1, 2

Protect Reset/Confirm

Write

X

47H

Write

0FFH

D0H

3

Lock Block/Confirm

Write

X

77H

Write

BA

D0H

1, 2, 4

Erase All Unlocked

Blocks

Write

X

A7H

Write

X

D0H

1, 2

Two-Byte Write

x8

Write

X

FBH

Write

A10

WD (L, H)

Write

WA

WD (H, L) 1, 2, 5