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LH28F008SA-85 Datasheet(PDF) 5 Page - Sharp Corporation |
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LH28F008SA-85 Datasheet(HTML) 5 Page - Sharp Corporation |
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5 / 27 page  8M (1M × 8) Flash Memory LH28F008SA 5 Commands are written using standard microproces- sor write timings. Command User Interface contents serve as input to the WSM, which controls the block erase and byte write circuitry. Write cycles also inter- nally latch addresses and data needed for byte write or block erase operations. With the appropriate command written to the register, standard microprocessor read timings output array data, access the intelligent identi- fier codes, or output byte write and block erase status for verification. The RY »/BY » output gives an additional indicator of WSM activity, providing capability for both hardware sig- nal of status (versus software polling) and status mask- ing (interrupt masking for background erase, for example). Status polling using RY »/BY » minimizes both CPU overhead and system power consumption. When low, RY »/BY » indicates that theWSM is performing a block erase or byte write operation. RY »/BY » high indicates that the WSM is ready for new commands, block erase is suspended or the device is in deep power down mode. Maximum access time is 85 ns (tACC) over the com- mercial temperature range (0°C to +70°C) and over VCC supply voltage range (4.5 V to 5.5 V and 4.75 V to 5.25 V). ICC active current (CMOS Read) is 20 mA typi- cal, 35 mA maximum at 8 MHz. When the CE » and PWD pins are at VCC, the ICC CMOS Standby mode is enabled. A Deep Powerdown mode is enabled when the PWD pin is at GND, minimizing power consumption and pro- viding write protection. ICC current in deep power down is 0.20 µA typical. Reset time of 400 ns is required from PWD switching high until outputs are valid to read attempts. Equivalently, the device has a wake time of 1 µs from PWD high until writes to the Command User Interface are recognized by the LH28F008SA.With PWD at GND, the WSM is reset and the Status Register is cleared. PRINCIPLES OF OPERATION The LH28F008SA includes on-chip write automation to manage write and erase functions. The Write State Machine allows for 100%TTL-level control inputs; fixed power supplies during block erasure and byte write; and minimal processor overhead with SRAM like interface timings. After initial device powerup, or after return from deep powerdown mode (see Bus Operations), the LH28F008SA functions as a read-only memory. Manipu- lation of external memory-control pins allow array read, standby and output disable operations. Both Status Register and intelligent identifiers can also be accessed through the Command User Interface whenVPP = VPPL. This same subset of operations is also available when high voltage is applied to the VPP pin. In addition, high voltage on VPP enables successful block erasure and byte writing of the device. All functions associated with altering memory contents - byte write, block erase, status and intelligent identifier - are accessed via the Command User Interface and verified through the Status Register. Figure 4. Memory Map MEMORY MAP FFFFF F0000 EFFFF E0000 DFFFF D0000 CFFFF C0000 BFFFF B0000 AFFFF A0000 9FFFF 90000 8FFFF 80000 7FFFF 70000 6FFFF 60000 5FFFF 50000 4FFFF 40000 3FFFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 00000 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 28F008SA-4 |
Similar Part No. - LH28F008SA-85 |
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Similar Description - LH28F008SA-85 |
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