LH5164A datasheet(7/11 Pages) SHARP

Part #	LH5164A

Description	CMOS 64K (8K x 8) Static RAM

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Manufacturer	SHARP [Sharp Corporation]

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DATA VALID

tDH

tDW

WE

DIN

(NOTE 6)

tCW

A0 - A12

OE

tWC

5164A-4

tWR

tCW

tAW

CE1

CE2

tAS

tOHZ

tWP

(NOTE 2)

tWR

(NOTE 3)

DOUT

(NOTE 5)

(NOTE 1)

tWR

HIGH-Z

1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP).

2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition,

to the time when the writing is finished.

3. tAS is defined as the time from address change to writing start.

4. tWR is defined as the time from writing finish to address change.

5. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the

outputs will remain high-impedance.

6. While I/O pins are in the output state, input signals with the opposite logic level must not be applied.

NOTES:

(NOTE 4)

Figure 6. Write Cycle 1

CMOS 64K (8K

× 8) Static RAM

LH5164A/AH

7

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