TIMING DIAGRAMS – READ CYCLE (cont’d)

Read Cycle No. 3

(Latched Address Controlled Read)

available. If the address is valid prior to the rising edge of

after ALE is HIGH (or if ALE is tied HIGH) then the access

data lines are in the Low-Z state but the data is not

ADDRESS

DQ

521028-4

VALID ADDRESS

PREVIOUS DATA

VALID DATA

ALE

Figure 6.

Read Cycle No. 3

CMOS 64K

×× 18 Static RAM

LH521028A

9