ISL80101

9

FN6931.1

August 31, 2011

Additional capacitors of any value in ceramic, POSCAP,

alum/tantalum electrolytic types may be placed in parallel to

improve PSRR at higher frequencies and/or load transient AC

output voltage tolerances.

INPUT CAPACITOR

For proper operation, a minimum capacitance of 10µF X5R/X7R

is required at the input. This ceramic input capacitor must be

longer than 0.5cm.

Power Dissipation and Thermals

The junction temperature must not exceed the range specified in

the “Recommended Operating Conditions (Notes 8, 9)” on

page 4. The power dissipation can be calculated by using

Equation 3:

maximum allowable power dissipation, as shown in Equation 4:

calculated from Equation 3, is less than the maximum allowable

The DFN package uses the copper area on the PCB as a heat-sink.

The EPAD of this package must be soldered to the copper plane

(GND plane) for effective heat dissipation. Figure 16 shows a curve

for the

Thermal Fault Protection

The power level and the thermal impedance of the package

(+45°C/W for DFN) determine when the junction temperature

exceeds the thermal shutdown temperature. In the event that the

die temperature exceeds around +160°C, the output of the LDO will

shut down until the die temperature cools down to about +130°C.

Current Limit Protection

The ISL80101 LDO incorporates protection against overcurrent due

to any short or overload condition applied to the output pin. The LDO

performs as a constant current source when the output current

exceeds the current limit threshold noted in the “Electrical

Specifications” table on page 4. If the short or overload condition is

regulation mode. In the event of an overload condition, the LDO may

begin to cycle on and off due to the die temperature exceeding

thermal fault condition and subsequently cooling down after the

power device is turned off.

–

×

+

×

=

(EQ. 3)

()

–

() θ

JA

⁄

=

(EQ. 4)

FIGURE 16. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB WITH

THERMAL VIAS

AREA ON PCB

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2468

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