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MS6258 Datasheet(PDF) 6 Page - MOSA ELECTRONICS |
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MS6258 Datasheet(HTML) 6 Page - MOSA ELECTRONICS |
6 / 17 page MOSA MS6258 Gain And Attenuation Volume Controller IC REV 6 6 www.mosanalog.com I 2C BUS DESCRIPTION Start and stop conditions A start condition is activated when the SCL is set to HIGH and SDA shifts from HIGH to LOW state. The stop condition is activated when SCL is set to HIGH and SDA shifts from LOW to HIGH state. Please refer to the timing diagram below. SDA SCL Start Stop SCL : Serial Clock Line, SDA : Serial Data Line Data validity A data on the SDA line is considered valid and stable only when the SCL signal is in HIGH state. The HIGH and LOW states of the SDA line can only change when the SCL signal is LOW. Please refer to the figure below. SDA SCL Data line stable, Data valid Data change allowed Byte format Every byte transmitted to the SDA line consists of 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transmitted first. Acknowledge During the Acknowledge clock pulse, the master (up) put a resistive HIGH level on the SDA line. The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during the Acknowledge clock pulse so that the SDA line is in a stable LOW state during this clock pulse. Please refer to the diagram below. SCL SDA MSB Acknowledge 12 3 7 8 9 Start The audio processor that has been addressed has to generate an Acknowledge after receiving each byte, otherwise, the SDA line will remain at the HIGH level during the ninth (9 th) clock pulse. In this case, the master transmitter can generate the STOP information in order to abort the transfer. |
Similar Part No. - MS6258_1 |
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Similar Description - MS6258_1 |
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