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LRS1331 Datasheet(PDF) 3 Page - Sharp Corporation |
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LRS1331 Datasheet(HTML) 3 Page - Sharp Corporation |
3 / 26 page Stacked Chip (16M Flash & 4M SRAM) LRS1331 Data Sheet 3 Table 1. Pin Descriptions PIN DESCRIPTION TYPE A0 to A16 Address Inputs (Common) Input F-A17 to F-A19 Address Inputs (Flash) Input S-A17 Address Input (SRAM) Input F-CE Chip Enable Input (Flash) Input S-CE1, S-CE2 Chip Enable Inputs (SRAM) Input F-WE Write Enable Input (Flash) Input S-WE Write Enable Input (SRAM) Input F-OE Output Enable Input (Flash) Input S-OE Output Enable Input (SRAM) Input S-LB SRAM Byte Enable Input (DQ0 to DQ7) Input S-UB SRAM Byte Enable Input (DQ8 to DQ15) Input F-RP Deep Power Down Input (Flash) Block erase and Word Write: VIH Read: VIH Deep Power Down: VIL Input F-WP Write Protect Input (Flash) Two Boot Blocks Locked: VIL Input F-RY/BY Ready/Busy Output(Flash) During an Erase or Write operation: VOL Block Erase and Word Write Suspend: HIGH-Z Deep Power Down: VOH Output DQ0 to DQ15 Data Input and Outputs (Common) Input/Output F-VCC Power Supply (Flash) Power S-VCC Power Supply (SRAM) Power F-VPP Write, Erase Power Supply (Flash) Block Erase and Word Write: F-VPP = VPPLK All Blocks Locked: F-VPP < VPPLK Power F-GND Ground (Flash) Power S-GND Ground (SRAM) Power NC No Connection — T1 to T5 Test Pins (Should be Open) — |
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