DRV8840

SLVSAB7B

– MAY 2010 – REVISED MAY 2011

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The DRV8840 supports fast decay and slow decay mode. Slow or fast decay mode is selected by the state of

the DECAY pin - logic low selects slow decay, and logic high sets fast decay mode. The DECAY pin has both an

internal pullup resistor of approximately 130 k

Ω and an internal pulldown resistor of approximately 80 kΩ. This

sets the mixed decay mode if the pin is left open or undriven.

DECAY mode also affects the operation of the bridge when it is disabled (by taking the ENBL pin inactive). This

applies if the ENABLE input is being used for PWM speed control of the motor, or if it is simply being used to

start and stop motor rotation.

If the DECAY pin is high (fast decay), when the bridge is disabled fast decay mode will be entered until the

current through the bridge reaches zero. Once the current is at zero, the bridge is disabled to prevent the motor

from reversing direction. This allows the motor to coast to a stop.

If the DECAY pin is low (slow decay), both low-side FETs will be turned on when ENBL is made inactive. This

essentially shorts out the back EMF of the motor, causing the motor to brake, and stop quickly. The low-side

FETs will stay in the ON state even after the current reaches zero.

Blanking Time

After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time

before enabling the current sense circuitry. This blanking time is fixed at 3.75

μs. Note that the blanking time also

sets the minimum on time of the PWM.

nRESET and nSLEEP Operation

The nRESET pin, when driven active low, resets the internal logic. It also disables the H-bridge driver. All inputs

are ignored while nRESET is active.

Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the

gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In

this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time

(approximately 1 ms) needs to pass before the motor driver becomes fully operational. Note that nRESET and

nSLEEP have internal pulldown resistors of approximately 100 k

Ω. These signals need to be driven to logic high

for device operation.

Protection Circuits

The DRV8840 is fully protected against undervoltage, overcurrent and overtemperature events.

Overcurrent Protection (OCP)

An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this

analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the

nFAULT pin will be driven low. The device will remain disabled until either nRESET pin is applied, or VM is

removed and re-applied.

Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor

winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense

Thermal Shutdown (TSD)

If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be

driven low. Once the die temperature has fallen to a safe level operation will automatically resume.

Undervoltage Lockout (UVLO)

If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the

threshold.

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© 2010–2011, Texas Instruments Incorporated