LPC1102 datasheet(9/39 Pages) NXP

Part #	LPC1102

Description	32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB SRAM

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Manufacturer	NXP [NXP Semiconductors]

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LPC1102

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Product data sheet

Rev. 4 — 24 June 2011

9 of 39

NXP Semiconductors

LPC1102

32-bit ARM Cortex-M0 microcontroller

Support for RS-485/9-bit mode allows both software address detection and automatic

address detection using 9-bit mode.

The UART includes a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.8.1 Features

• Maximum UART data bit rate of 3.125 Mbit/s.

• 16 Byte Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• FIFO control mechanism that enables software flow control implementation.

• Support for RS-485/9-bit mode.

7.9 SPI serial I/O controller

The LPC1102 contains one SPI controller and fully supports SSP features.

The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. Only a single master and a single

slave can communicate on the bus during a given data transfer. The SPI supports full

duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the

slave and from the slave to the master. In practice, often only one of these data flows

carries meaningful data.

Remark: Care must be taken when using the SPI because the SPI clock SCK and the

serial wire debug clock SWCLK share the same pin on the WLCSP16 package. Once the

SPI is enabled, the serial wire debugger is no longer available.

7.9.1 Features

• Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

7.10 10-bit ADC

The LPC1102 contains one ADC. It is a single 10-bit successive approximation ADC with

five channels.

7.10.1 Features

• 10-bit successive approximation ADC.

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