DS18B20-PAR

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and then compare this value to either the ROM code CRC (for ROM reads) or to the scratchpad CRC (for

scratchpad reads). If the calculated CRC matches the read CRC, the data has been received error free. The

comparison of CRC values and the decision to continue with an operation are determined entirely by the

bus master. There is no circuitry inside the DS18B20-PAR that prevents a command sequence from

proceeding if the DS18B20-PAR CRC (ROM or scratchpad) does not match the value generated by the

bus master.

The equivalent polynomial function of the CRC (ROM or scratchpad) is: CRC = X

The bus master can re-calculate the CRC and compare it to the CRC values from the DS18B20-PAR

using the polynomial generator shown in Figure 8. This circuit consists of a shift register and XOR gates,

and the shift register bits are initialized to 0. Starting with the least significant bit of the ROM code or the

least significant bit of byte 0 in the scratchpad, one bit at a time should shifted into the shift register.

After shifting in the 56

polynomial generator will contain the re-calculated CRC. Next, the 8-bit ROM code or scratchpad CRC

from the DS18B20-PAR must be shifted into the circuit. At this point, if the re-calculated CRC was

correct, the shift register will contain all 0s. Additional information about the Dallas 1-Wire cyclic

redundancy check is available in Application Note 27 entitled “Understanding and Using Cyclic

Redundancy Checks with Dallas Semiconductor Touch Memory Products.”

CRC GENERATOR Figure 8

1-WIRE BUS SYSTEM

The 1-Wire bus system uses a single bus master to control one or more slave devices. The DS18B20-

PAR is always a slave. When there is only one slave on the bus, the system is referred to as a “single-

drop” system; the system is “multi-drop” if there are multiple slaves on the bus.

All data and commands are transmitted least significant bit first over the 1-Wire bus.

The following discussion of the 1-Wire bus system is broken down into three topics: hardware

configuration, transaction sequence, and 1-Wire signaling (signal types and timing).

HARDWARE CONFIGURATION

The 1-Wire bus has by definition only a single data line. Each device (master or slave) interfaces to the

data line via an open drain or 3–state port. This allows each device to “release” the data line when the

device is not transmitting data so the bus is available for use by another device. The 1-Wire port of the

DS18B20-PAR (the DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 9.

The 1-Wire bus requires an external pullup resistor of approximately 5 k

Ω; thus, the idle state for the 1-

Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle

state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-Wire

bus is in the inactive (high) state during the recovery period. If the bus is held low for more than 480

μs,

all components on the bus will be reset. In addition, to assure that the DS18B20-PAR has sufficient

supply current during temperature conversions, it is necessary to provide a strong pullup (such as a

MOSFET) on the 1-Wire bus whenever temperature conversions or EEPROM writes are taking place (as

described in the PARASITE POWER section).

(MSB)

(LSB)

XOR

XOR

XOR

INPUT