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ISL706BRHVX Datasheet(PDF) 10 Page - Intersil Corporation |
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ISL706BRHVX Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 15 page ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH 10 FN7662.0 September 15, 2011 Functional Overview The ISL705xRH and ISL706xRH provide the functions needed for monitoring critical voltages in high reliability applications such as microprocessor systems. Functions of the these supervisors include power-on reset control; supply voltage supervisions; power-fail detection; manual-reset assertion and a watch dog timer. The integration of all these functions along with their high threshold accuracy, low power consumption, and radiation tolerance make these devices ideal for critical supply monitoring. Reset Output Reset control has long been a critical aspect of embedded control design. Microprocessors require a reset signal during power up to ensure that the system environment is stable before initialization. The reset signal provides several benefits: • It prevents the system microprocessor from starting to operate with insufficient voltage. • It prevents the processor from operating prior to stabilization of the oscillator. • It ensures that the monitored device is held out of operation until internal registers are initialized. • It allows time for an FPGA to perform its self configuration prior to initialization of the circuit. On power-up, once VDD reaches 1.2V, RST is guaranteed logic low. As VDD rises, RST stays low. When VDD rises above the reset threshold (VRST), an internal timer releases RST after 200ms (typ). RST pulses low whenever VDD degrades to below VRST (see Figure 3). If a brownout condition occurs in the middle of a previously initiated reset pulse, the pulse is lengthened 200ms (typ). On power-down, once VDD falls below the reset threshold, RST stays low and is guaranteed to be low until VDD drops below 1.2V. The ISL705BRH and ISL706BRH active-high RST output is simply the complement of the RST output, and is guaranteed to be valid with VDD down to 1.2V. The ISL705CRH and ISL706CRH active-low open-drain reset output is functionally identical to RST. Power Failure Monitor Besides monitoring VDD for reset control, these devices have a Power-Failure Monitor feature that supervises an additional critical voltage on the Power-Fail Input (PFI) pin. For example, the PFI pin could be used to provide an early power-fail warning, overvoltage detection or monitor a power supply other than VDD. PFO goes low whenever PFI is less than VPFI. The threshold detector can be adjusted using an external resistor divider network to provide custom voltage monitoring for voltages greater than VPFI, according to Equation 1 (see Figure 14). Manual Reset The manual reset input (MR) allows designers to add manual system reset capability via a push button switch (see Figure 15). The MR input is an active low debounced input which asserts reset if the MR pin is pulled low to less than VIL for at least 150ns. After MR is released, the reset output remains asserted for tRST and then released. MR is a TTL/CMOS logic compatible, so it can be driven by external logic. By connecting WDO to MR, one can force a watchdog time out to generate a reset pulse. Watch Dog Timer The watchdog time circuit checks for coherent program execution by monitoring the WDI pin. If the processor does not toggle the watchdog input within tWD (1.0s min), WDO will go low. As long as reset is asserted or the WDI pin is tri-stated, the watchdog timer will stay cleared and not count. As soon as reset is released and WDI is driven high or low, the timer will start counting. Pulses as short as 50ns can be detected on the ISL705xRH, on ISL706xRH pulses as short as 100ns can be detected. Whenever there is a low-voltage VDD condition, WDO goes low. Unlike the reset outputs, however, WDO goes high as soon as VDD rises above its voltage trip point (see Figure 4). With WDI open or connected to a tri-stated high impedance input, the Watchdog Timer is disabled and only pulls low when VDD < VRST. Applications Information Negative Voltage Sensing This family of devices can be used to sense and monitor the presence of both a positive and negative rail. VDD is used to monitors the positive supply while PFI monitors the negative rail. PFO is high when the negative rail degrades below a VTRIP value and remains low when the negative rail is above the Vtrip value. As the differential voltage across the R1, R2 divider is increased, the resistor values must be chosen such that the PFI node is <1.25V when the -V supply is satisfactory and the positive supply VIN VPFI R1 R2 + R2 ---------------------- ⎝⎠ ⎛⎞ = (EQ. 1) FIGURE 14. CUSTOM VTH WITH RESISTOR DIVIDER ON PFI VIN R1 R2 PFI ISL705xRH/ISL706xRH MR PB 20k FIGURE 15. CONNECTING A MANUAL RESET PUSH-BUTTON ISL705xRH/ISL706xRH |
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