8

FN6665.5

May 13, 2011

Pin Descriptions

PIN NUMBER

NAME

FUNCTION

28 LD

32 LD

1

1

PGOOD2 SMPS2 open-drain power-good status output. Connect to LDO5 through a 100kΩ resistor. Output will be high when

the SMPS2 output is within the regulation window with no faults detected.

2

2

FSET2

Frequency control input for SMPS2. Connect a resistor to ground to program the switching frequency. A small

ceramic capacitor such as 10nF is necessary to parallel with this resistor to smooth the voltage.

3

3

FCCM

Logic input to control efficiency mode. Logic high forces continuous conduction mode (CCM). Logic low allows full

discontinuous conduction mode (DCM). Float this pin for ultrasonic DCM operation.

4

4

VCC2

SMPS2 analog power supply input for reference voltages and currents. Connect to VCC1 with a 10

 resistor.

Bypass to ground with a 1µF ceramic capacitor near the IC.

5

5

VCC1

SMPS1 analog power supply input for reference voltages and currents. It is internally connected to the LDO5

output. Bypass to ground with a 1µF ceramic capacitor near the IC.

-

6

LDO3EN Logic input for enabling and disabling the LDO3 linear regulator. Positive logic input.

6

7

FSET1

Frequency control input for SMPS1. Connect a resistor to ground to program the switching frequency. A small

ceramic capacitor such as 10nF is necessary to parallel with this resistor to smooth the voltage.

7

8

PGOOD1 SMPS1 open-drain power-good status output. Connect to LDO5 through a 100kΩ resistor. Output will be high when

the SMPS1 output is within the regulation window with no faults detected.

8

9

FB1

SMPS1 feedback input used for output voltage programming and regulation.

9

10

VOUT1

SMPS1 output voltage sense input. Used for soft-discharge.

10

11

ISEN1

11

12

OCSET1 Input from current-sensing network used to program the overcurrent shutdown threshold for SMPS1.

12

13

EN1

Logic input to enable and disable SMPS1. A logic high will enable SMPS1 immediately. A logic low will disable

SMPS1. Floating this input will delay SMPS1 start-up until after SMPS2 achieves regulation.

13

14

PHASE1 SMPS1 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching

NMOS source, the synchronous NMOS drain, and the output inductor for SMPS1.

14

15

UGATE1 High-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 switching FET.

15

16

BOOT1

SMPS1 bootstrap input for the switching NMOS gate drivers. Connect to PHASE1 with a 0.22µF ceramic capacitor.

16

17

LGATE1 Low-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 synchronous FET.

-

18

LDO3FB LDO3 linear regulator feedback input used for output voltage programming and regulation.

-

19

LDO3

LDO3 linear regulator output, providing up to 100mA. Bypass to ground with a 4.7µF ceramic capacitor.

-

20

LDO3IN

Power input for LDO3. Must be connected to a voltage greater than the LDO3 set point plus the dropout voltage.

17

21

VIN

Feed-forward input for line voltage transient compensation. Connect to the power train input voltage.

18

22

LDO5

5V linear regulator output, providing up to 100mA before switchover to SMPS2. Bypass to ground with a 4.7µF

ceramic capacitor.

19

23

PGND

Power ground for SMPS1 and SMPS2. This provides a return path for synchronous FET switching currents.

20

24

LGATE2 Low-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 synchronous FET.

21

25

BOOT2

SMPS2 bootstrap input for the switching NMOS gate drivers. Connect to PHASE2 with a 0.22µF ceramic capacitor.

22

26

UGATE2 High-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 switching FET.

23

27

PHASE2 SMPS2 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching

NMOS source, the synchronous NMOS drain, and the output inductor for SMPS2.

24

28

EN2

Logic input to enable and disable SMPS2. A logic high will enable SMPS2 immediately. A logic low will disable

SMPS2. Floating this input will delay SMPS2 start-up until after SMPS1 achieves regulation.

25

29

OCSET2 Input from current-sensing network used to program the over-current shutdown threshold for SMPS2.

26

30

ISEN2

27

31

VOUT2

SMPS2 output voltage sense input. Used for soft-discharge and switchover to LDO5 output.

ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C