DS2417

1–WIRE SIGNALING

The DS2417 requires strict protocols to ensure data integrity. The protocol consists of four types of sig-

naling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, and Read

Data. Except for the presence pulse the bus master initiates all these signals.

The initialization sequence required to begin any communication with the DS2417 is shown in Figure 8.

A reset pulse followed by a presence pulse indicates the DS2417 is ready to send or receive data. The bus

goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor. After

INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 8

RESISTOR

MASTER

DS2417

MASTER RX "PRESENCE PULSE"

60  t

MASTER TX

"RESET PULSE"

PULLUP MIN

0V

V

*

ways be less than 960µs.

**

Includes recovery time

READ/WRITE TIME SLOTS

The definitions of write and read time slots are illustrated in Figure 9. The master initiates all time slots

by driving the data line low. The falling edge of the data line synchronizes the DS2417 to the master by

triggering an internal delay circuit. During write time slots, the delay circuit determines when the

DS2417 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit

determines how long the DS2417 will hold the data line low. If the data bit is a “1”, the DS2417 will not

hold the data line low at all.

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