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MAX2838 Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX2838 Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 22 page 3.3GHz to 3.9GHz Wireless Broadband RF Transceiver 8 _______________________________________________________________________________________ Note 1: Min and max limits are guaranteed by test above TA = +25°C and are guaranteed by design and characterization at TA = -40°C. The power-on register settings are not guaranteed. Recommended register setting must be loaded after VCC is supplied. Note 2: Two tones at +20MHz and +39MHz offset with -35dBm/tone. Measure IM3 at 1MHz. Note 3: Gain adjusted over max gain and max gain - 3dB. Note 4: VCC rise time (0V to 2.7V) must be less than 1ms. AC ELECTRICAL CHARACTERISTICS—TIMING (MAX2838 Evaluation Kit, VCC = 2.8V, fLO = 3.6GHz, fREF = 40MHz, CS = high, SCLK = DIN = low, PLL loop bandwidth = 180kHz, and TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SYSTEM TIMING Automatic VCO sub-band selection 2 ms Channel Switching Time Frequency error settles to ±50Hz Manual VCO sub-band selection 56 µs Rx to Tx 2 Turnaround Time Measured from Tx or Rx enable rising edge, signal settling to within 0.5dB of steady state Tx to Rx 2 µs Tx Turn-On Time (from Standby Mode) Measured from Tx enable rising edge, signal settling to within 0.5dB of steady state 2µs Tx Turn-Off Time (to Standby Mode) From Tx-enable falling edge 0.1 µs Rx Turn-On Time (from Standby Mode) Measured from Rx enable rising edge, signal settling to within 0.5dB of steady state 2µs Rx Turn-Off Time (to Standby Mode) From Rx-enable falling edge 0.1 µs 4-WIRE SERIAL INTERFACE TIMING (See Figure 1) SCLK Rising Edge to CS Falling Edge Wait Time tCSO 6ns Falling Edge of CS to Rising Edge of First SCLK Time tCSS 6ns DIN to SCLK Setup Time tDS 6ns DIN to SCLK Hold Time tDH 6ns SCLK Pulse-Width High tCH 6ns SCLK Pulse-Width Low tCL 6ns Last Rising Edge of SCLK to Rising Edge of CS or Clock to Load Enable Setup Time tCSH 6ns CS High Pulse Width tCSW 20 ns Time Between Rising Edge of CS and the Next Rising Edge of SCLK tCS1 6ns Clock Frequency fCLK 45 MHz Rise Time tR fCLK / 10 ns Fall Time tF fCLK / 10 ns SCLK Falling Edge to Valid DOUT tD 12.5 ns |
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