Detailed Description

Register Descriptions

The MAX3541 includes 11 programmable registers and

2 read-only registers. The 11 programmable registers

include two N-divider registers, an R-divider register, a

VCO register, an IFOVLD/Charge Pump/Filter Select

register, a Control register, a Shutdown register, and

Tracking Filter Control registers. These 11 programma-

ble registers are also readable. The read-only registers

include a status register and a ROM table data register.

Recommended default bit settings are provided for

user convenience only and are not guaranteed. The

user must write all registers after power-up and no ear-

lier than 100μs after power-up.

Complete Single-Conversion

Television Tuner

10

______________________________________________________________________________________

MSB

LSB

DATA BYTE

REGISTER

NAME

READ/

WRITE

REGISTER

ADDRESS

D7

D6

D5

D4

D3

D2

D1

D0

N-DIV High

Both

0x00

0

N14

N13

N12

N11

N10

N9

N8

N-DIV Low

Both

0x01

N7

N6

N5

N4

N3

N2

N1

N0

R-DIV

Both

0x02

0

R6

R5

R4

R3

R2

R1

R0

VCO

Both

0x03

VCO4

VCO3

VCO2

VCO1

VCO0

LD

VDIV1

VDIV0

IFOVLD,

Charge Pump,

and Filter Select

Both

0x04

0

IFOVLD2

IFOVLD1

IFOVLD0

CP1

CP0

TF

0

Control

Both

0x05

0

0

0

0

SHDN

_RF

SHDN

_IFVGA

INPT1

INPT0

Shutdown

Both

0x06

SHDN

_MIX1

SHDN

_MIX0

SHDN

_IF

SHDN

_OD

SHDN

_SYN

000

Tracking Filter

Series Capacitor

Both

0x07

TFS7

TFS6

TFS5

TFS4

TFS3

TFS2

TFS1

TFS0

Tracking Filter

Parallel Capacitor

Both

0x08

FLD

0

TFP5

TFP4

TFP3

TFP2

TFP1

TFP0

Tracking Filter

ROM Address

Both

0x09

0

0

0

0

TFA3

TFA2

TFA1

TFA0

Reserved

Both

0x0A

X

X

X

X

X

X

X

X

ROM Table

Data Readback

Read

0x0B

TFR7

TFR6

TFR5

TFR4

TFR3

TFR2

TFR1

TFR0

Status

Read

0x0C

POR

LD2

LD1

LD0

X

X

X

X

Table 1. Register Configuration

BIT NAME

BIT LOCATION (0 = LSB)

RECOMMENDED

DEFAULT

FUNCTION

RESERVED

7

0

Must be set to 0.

N[14:8]

6-0

0000001

Sets the most significant bits of the PLL integer divider (N). Default

integer divider value is N = 4688. N can range from 256 to 32,767.

Table 2. N-DIV High Register (Address: 0000b)