Depending on the input clock frequency of 77.76MHz,

155.52MHz, or 622.08MHz, the clock divider ratio must

be set to 1, 2, or 8, respectively. The POUT output

buffer is preceded by a clock divider that scales the

main clock output by 1, 2, 4, or 8 to provide an optional

clock.

LOL Detection Circuitry

The MAX3670 incorporates a loss-of-lock (LOL) monitor

that consists of an XOR gate, filter, and comparator

with adjustable threshold (see “LOL Setup” in the

Applications section). A loss-of-lock condition is sig-

naled with a TTL low when the reference clock frequen-

cy differs from the VCO frequency.

Gain-Control Logic

The gain-control circuitry facilitates the tuning of the

loop bandwidth by setting phase-detector gain and fre-

quency-divider ratio. The gain-control logic can be pro-

grammed to divide from 1 to 1024, in binary multiples,

and to adjust the phase detector gain to 5µA/UI or

20µA/UI (see Table 3 in

Setting the Loop Bandwidth

section).

Phase-Frequency Detector and

Charge Pump

The phase-frequency detector incorporated into the

MAX3670 produces pulses proportional to the phase

difference between the reference clock and the VCO

input. The charge pump converts this pulse train to a

current signal that is fed to the op amp.

Op Amp

The op amp is used to form an active PLL loop filter

capable of driving the VCO control voltage input. Using

the POLAR input, the op amp input polarity can be select-

ed to work with VCOs having positive or negative gain-

transfer functions. The COMP pin selects the op amp

internal compensation. Connect COMP to ground if the

Design Procedure

Setting Up the VCO and

Reference Clock

The MAX3670 accepts 77.76MHz, 155.52MHz, or

622.08MHz (including FEC rates) reference clock fre-

quencies. The RSEL input must be set so that the refer-

ence clock is prescaled to 77.76MHz (or FEC rate), to

provide the proper range for the PFD and LOL detec-

tion circuitry. Table 1 shows the divider ratio for the dif-

ferent reference frequencies.

The MAX3670 is designed to accept 77.76MHz,

155.52MHz, or 622.08MHz (including FEC rates) volt-

age-controlled oscillator (VCO) frequencies. The VSEL

input must be set so that the VCO input is prescaled to

77.76MHz (or FEC rate), to provide the proper range for

the PFD and LOL detection circuitry. Table 2 shows the

divider ratio for the different VCO frequencies.

Setting the Loop Bandwidth

To eliminate jitter present on the reference clock, the

proper selection of loop bandwidth is critical. If the total

output jitter is dominated by the noise at the reference

clock input, then lowering the loop bandwidth will

reduce system jitter. The loop bandwidth (K) is a func-

width of the MAX3670 can be approximated by

For stability, a zero must be added to the loop in the form

Diagram). The location of the zero can be approximated as

Due to the second-order nature of the PLL jitter trans-

certain applications, it may be desirable to limit jitter

f

RC

π

1

2

11

K

KR K

N

PD

VCO

=

π

1

2

Low-Jitter 155MHz/622MHz

Clock Generator

8

_______________________________________________________________________________________

INPUT

PIN

RSEL

REFERENCE

CLOCK INPUT

FREQ. (MHz)

DIVIDER

PREDIVIDER

OUTPUT

FREQ. (MHz)

77.76

1

77.76

OPEN

155.52

2

77.76

GND

622.08

8

77.76

Table 1. Reference Clock Divider

INPUT

PIN

VSEL

VCO CLOCK

INPUT FREQ.

(MHz)

DIVIDER

PREDIVIDER

OUTPUT

FREQ. (MHz)

77.76

1

77.76

OPEN

155.52

2

77.76

GND

622.08

8

77.76

Table 2. VCO Clock Divider