10-Bit, Nonvolatile, Linear-Taper Digital

Potentiometers

4

_______________________________________________________________________________________

TIMING CHARACTERISTICS

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

ANALOG SECTION

MAX5481

5

Wiper Settling Time (Note 6)

MAX5482

22

µs

SPI-COMPATIBLE SERIAL INTERFACE (Figure 3)

SCLK Frequency

7

MHz

SCLK Clock Period

140

ns

SCLK Pulse-Width High

60

ns

SCLK Pulse-Width Low

60

ns

CS Fall to SCLK Rise Setup

60

ns

SCLK Rise to CS Rise Hold

0ns

DIN to SCLK Setup

40

ns

DIN Hold after SCLK

0ns

SCLK Rise to CS Fall Delay

15

ns

CS Rise to SCLK Rise Hold

60

ns

CS Pulse-Width High

150

ns

Write NV Register Busy Time

12

ms

UP/DOWN DIGITAL INTERFACE (Figure 8)

CS to INC Setup

25

ns

INC High to U/D Change

20

ns

U/D to INC Setup

25

ns

INC Low Period

25

ns

INC High Period

25

ns

INC Inactive to CS Inactive

50

ns

CS Deselect Time (Store)

50

ns

INC Cycle Time

50

ns

INC Active to CS Inactive

50

ns

Wiper Store Cycle

12

ms

nal (W) is unloaded and measured with a high-input-impedance voltmeter.

nal is driven with a source current of 40µA for the 50kΩ device and 200µA for the 10kΩ device.

Note 4: The wiper resistance is measured using the source currents given in Note 3.

0.5V). See Supply Current vs. Digital Input Voltage in the

Typical Operating Characteristics.

Note 6: Wiper settling test condition uses the voltage-divider configuration with a 10pF load on W. Transition code from 00000 00000

to 01111 01111 and measure the time from

CS going high to the wiper voltage settling to within 0.5% of its final value.