DDR VDDQ and VTT Termination Voltage Regulator

TJ3212

Mar. 2011 - Preliminary

- 6

-

HTC

ELECTRICAL CHARACTERISTICS

Parameters

Symbol

Condition

Min.

Typ.

Max.

Unit

Supply Voltage Range

3.0

3.6

V

Quiescent Current

2

mA

ADJSD Voltage

(3)

1.225

1.250

1.275

V

Shutdown Current

0.1

mA

ADJSD Logic High

SHDN_H

(2)

2.7

V

ADJSD Logic Low

SHDN_L

(3)

1.5

V

Under-voltage Lockout

UVLO

Hysteresis = 100mV

(3)

2.40

2.70

2.90

V

Thermal SHDN Threshold

(3)

150

170

°C

Thermal SHDN Hysteresis

50

°C

TEMPCO

(3)

100

ppm/°C

VDDQ Regulator

VDDQ Output Voltage

2.450

2.500

2.550

V

VDDQ Load Regulation

(4)

10

25

mV

VDDQ Line Regulator

5

25

mV

VDDQ Dropout Voltage

(5)

500

mV

ADJSD Bias Current

(3)

0.8

3

uA

VDDQ Current Limit

2.0

2.5

A

VTT Regulator

VTT Output Voltage

1.225

1.250

1.275

V

VTT Load Regulation

(4)

(4)

-30

10

-10

30

mV

mV

VTT Line Regulator

5

15

mV

ITT Current Limit

Source / Sink

(4)

± 2.0

± 2.5

A

VTT Shutdown Leakage

Current

10

uA

Reference Voltage

1.225

1.250

1.275

V

Note 1. VIN = 3.3V, VDDQ = 2.50V, VTT = 1.25V (default values), CDDQ=CTT=47 F, TA = 25°C unless otherwise specified.

Note 2. The ADJSD Logic High value is normally satisfied for full input voltage range by using a low leakage current (below 1 A).

Schottky diode at ADJSD control pin.

Note 3. Guaranteed by design.

Note 4. Load and line regulation are measured at constant junction temperature by using pulse testing with a low duty cycle. For high current

tests, correlation method can be used. Changes in output voltage due to heating effects must be taken into account separately. Load

and line regulation values are guaranteed by design up to the maximum power dissipation.

Note 5. Dropout voltage is the input to output voltage differential at which output voltage has dropped 100mV from the nominal value obtained

at 3.3V input. It depends on load current and junction temperature. Guaranteed by design.