MC74HCT138A

High–Speed CMOS Logic Data

DL129 — Rev 6

3

MOTOROLA

Symbol

Parameter

Guaranteed Limit

Unit

Symbol

Parameter

– 55 to

25

_C

v 85_C

v 125_C

Unit

tPLH,

tPHL

Maximum Propagation Delay, Input A to Output Y

(Figures 1 and 4)

30

38

45

ns

tPLH,

tPHL

Maximum Propagation Delay, CS1 to Output Y

(Figures 2 and 4)

27

34

41

ns

tPLH,

tPHL

Maximum Output Transition Time, CS2 or CS3 to Output Y

(Figures 3 and 4)

30

38

45

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 2 and 4)

15

19

22

ns

tr, tf

Maximum Input Rise and Fall Time

500

500

500

ns

Cin

Maximum Input Capacitance

10

10

10

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Enabled Output)*

Typical @ 25

°C, VCC = 5.0 V

pF

CPD

Power Dissipation Capacitance (Per Enabled Output)*

51

pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

EXPANDED LOGIC DIAGRAM

A0

A1

A2

CS3

CS2

CS1

1

2

3

4

5

6

15

14

13

12

11

10

9

7

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y0