8

8 - 10

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Synchronous Programming

For applications which can not tolerate a momentary undefined division ratio, which normally occurs while changing

the data bits (A0-A4) at random, synchronous programming can be used. Data is loaded into the counter on every

rising edge of the clock which occurs while the output (OUT) is “HIGH”. The typical minimum setup and hold times are

shown in the table below as a function of frequency. For precision applications, the rising edge of the complementary

output may be used to latch the new data bits (A0-A4), so that all bits are settled before the next load cycle.

T

SETTLING MAX

= N/f

IN

(For Synchronous Programming)

Where N is the desired division ratio, and f

IN

= Input Frequency (Hz)

Programmable Divider Timing Requirements

for Synchronous Programming

IN

OUT

OUT

C UR R E NT DAT A

NE W DAT A

A0-A4

t

SU

t

HOLD

Data Load

Ris ing E dge

Ris ing E dge to

Clock New Data

Parameter

0.5 GHz

1 GHz

2 GHz

t

SETUP

200 ps

200 ps

200 ps

t

HOLD

700 ps

300 ps

120 ps

v03.0808

2.8 GHz INTEGER-N SYNTHESIZER

(N = 2 - 32)