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ICS9147-22 Datasheet(PDF) 4 Page - Integrated Device Technology |
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ICS9147-22 Datasheet(HTML) 4 Page - Integrated Device Technology |
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4 / 7 page  4 ICS9147-22 Technical Pin Function Descriptions VDD(1,2,3,4) This is the power supply to the internal core logic of the device as well as the clock output buffers for REF(0:1), PCICLK,48/24MHzandSDRAM(0:7). This supply operates at 3.3 volts. Clocks from the listed buffers that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the Clocks, please consult the DC parameter table in this data sheet. VDDL This is the power supply for the CPUCLK and IOAPIC output buffers. The voltage level for these outputs may be 2.5 or 3.3 volts. Clocks from the buffers that each supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels of these Clocks, please consult the DC parameter table in this Data Sheet. GND This is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. X1 This input pin serves one of two functions. When the device is used with a Crystal, X1 acts as the input pin for the reference signal that comes from the discrete crystal. When the device is driven by an external clock signal, X1 is the device input pin for that reference clock. This pin also implements an internal Crystal loading capacitor that is connected to ground. See the data tables for the value of this capacitor. Also includes feedback resistor from X2. X2 This Output pin is used only when the device uses a Crystal as the reference frequency source. In this mode of operation, X2 is an output signal that drives (or excites) the discrete Crystal. The X2 pin will also implement an internal Crystal loading capacitor that is connected to ground. See the Data Sheet for the value of this capacitor. CPUCLK (0:3) These Output pins are the Clock Outputs that drive processor and other CPU related circuitry that requires clocks which are in tight skew tolerance with the CPU clock. The voltage swing of these Clocks is controlled by the Voltage level applied to theVDDL2 pin of the device. See the Functionality Table for a list of the specific frequencies that are available for these Clocks and the selection codes to produce them. SDRAM(0:7) These Output Clocks are use to drive Dynamic RAMs and are low skew copies of the CPU Clocks. The voltage swing of the SDRAMs output is controlled by the supply voltage that is applied to VDD3 of the device, operating at 3.3 volts. 48MHz This is a fixed frequency Clock output at 48MHz that is typically used to drive USB devices. 24MHz This pin is a fixed frequency clock output typically used to drive Super I/O devices. IOAPIC This Output is a fixed frequency Output Clock that runs at the Reference Input (typically 14.31818MHz) . Its voltage level swing is controlled by VDDL and may operate at 2.5 or 3.3volts. REF(0:1) The REF Outputs are fixed frequency Clocks that run at the same frequency as the Input Reference Clock X1 or the Crystal (typically 14.31818MHz) attached across X1 and X2. PCICLK_F This Output is equivalent to PCICLK(0:5) and is FREE RUNNING. PCICLK (0:5) These Output Clocks generate all the PCI timing requirements for a Pentium/Pro based system. They conform to the current PCI specification. They run at 1/2 CPU frequency, or CPU/2.5; see frequency table. FS0,1,2 These Input pins control the frequency of the Clocks at the CPU, PCICLK and SDRAM output pins. See frequency table. PD# This input pin stops all clocks in the low state and powers down the oscillator and VCOs. |
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