ICS8743008I

FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR

PRELIMINARY

IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 9

ICS8743008DKI REV. A AUGUST 25, 2008

NOTE 1: Outputs termination with 50

Ω to V

AC Electrical Characteristics

NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the differential cross points.

NOTE 3: Please refer to the Phase Noise plots.

NOTE 4: RMS jitter after applying system transfer function. See IDT Application Note PCI Express Reference Clock Requirements.

Maximum limit for PCI Express is 86ps peak-to-peak.

NOTE 5: RMS jitter after applying system transfer function. The pole frequencies for H1 and H2 for PCIe Gen 2 are 8-16MHz and

5-16MHz. See IDT Application Note PCI Express Reference Clock Requirements. Maximum limit for PCI Express Generation 2 is 3.1ps

rms.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Output High Current; NOTE 1

µA

Output Low Current; NOTE 1

µA

Peak-to-Peak Output Voltage Swing

0.6

1.0

V

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

Units

Output Frequency

98

160

MHz

tjit(cc)

Cycle-to-Cycle Jitter; NOTE 1

25

ps

tsk(o)

Output Skew; NOTE 2

60

ps

tjit(Ø)

RMS Phase Jitter (Random);

NOTE 3

125MHz, Integration Range:

1.875MHz – 20MHz

0.60

ps

100MHz, Integration Range:

1.875MHz – 20MHz

0.66

ps

Phase Jitter Peak-to-Peak;

NOTE 4

125MHz, (1.2MHz – 21.9MHz),

13.49

ps

125MHz

1.29

ps

Output Rise/Fall Time

20% to 80%

600

ps

odc

Output Duty Cycle

50

%