MC100ES8014 datasheet(4/7 Pages) IDT

Part #	MC100ES8014

Description	Low Voltage 1:5 Differential LVDS Clock Fanout Buffer

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Manufacturer	IDT [Integrated Device Technology]

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MC100ES8014

MOTOROLA

4

TIMING SOLUTIONS

Table 6. AC Characteristics (VCC = 3.3V±5%; TJ = 0°C to 110°C)

1 2

1.

AC characteristics are design targets and pending characterization.

2.

AC characteristics apply for parallel output termination of 50

Ω to V

TT.

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

HSTL/LVDS differential input signals (CLK0, CLK0)

VDIF

Differential input voltage (peak-to-peak)3

3.

VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew.

0.4

V

VX, IN

Differential cross point voltage4

4.

VX (AC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (AC) range

and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF(AC) impacts the device propagation delay, device and

part-to-part skew.

0.68

0.9

V

fCLK

Input Frequency

0 – 400

TBD

MHz

Differential

tPD

Propagation Delay

TBD

ps

Differential

PECL differential input signals (CLK1, CLK1)

VPP

Differential input voltage (peak-to-peak)5

5.

VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew.

0.2

1.0

V

VCMR

Differential cross point voltage6

6.

VCMR (AC) is the crosspoint of the differential PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC)

range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP(AC) impacts the device propagation delay, device

and part-to-part skew.

1VCC – 0.6

V

fCLK

Input Frequency

0 – 400

MHz

Differential

tPD

Propagation Delay

TBD

ps

Differential

HSTL clock outputs (Q[0:4], Q[0:4])

VX, OUT

Output differential crosspoint

0.68

0.75

0.9

V

VOH

Output high voltage

1

V

VOL

Ouput low voltage

0.5

V

VO(P-P)

Differential output voltage (peak-to-peak)

0.5

V

tSK(O)

Output-to-output skew

50

ps

Differential

tSK(PP)

Output-to-output skew (part-to-part)

TBD

ps

Differential

tJIT(CC)

Output cycle-to-cycle jitter

TBD

DCO

Output duty cycle

TBD

50

TBD

%

DCfref = 50%

tr / tf

Output Rise/Fall Times

0.05

TBD

ns

20% to 80%

tPDL

Output disable time7

7.

Propagation delay EN deassertion to differential output disabled (differential low: true output low, complementary output high).

2.5*T +tPD

3.5*T +tPD

ns

T = CLK period

tPLD

Output enable time8

8.

Propagation delay EN assertion to output enabled (active).

3*T +tPD

4*T +tPD

ns

T = CLK period

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC100ES8014

Low Voltage 1:5 Differential LVDS Clock Fanout Buffer

NETCOM

IDT™ Low Voltage 1:5 Differential LVDS Clock Fanout Buffer

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MC100ES8014

4

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