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HMC677LP5 Datasheet(PDF) 2 Page - Hittite Microwave Corporation |
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HMC677LP5 Datasheet(HTML) 2 Page - Hittite Microwave Corporation |
2 / 8 page 5 5 - 2 For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com Serial Control Interface Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) The HMC677LP5(E) contains a 3-wire SPI compatible digital interface (DATA, CLK, LE). It is activated when P/S is kept high. The 6-bit serial word must be loaded MSB first. The positive-edge sensitive CLK and LE requires clean transitions. Standard logic families work well. When LE is high, 6-bit data in the serial input register is transferred to the outputs. When LE is high CLK is masked to prevent data transition during output loading. When P/S is low, 3-wire SPI interface inputs (DATA, CLK, LE) are disabled and the serial input register is loaded asynchronously with parallel digital inputs (I0-I5). When LE is high, 6-bit parallel data is transferred. For all modes of operations, the outputs will stay constant while LE is kept low. Note: The parallel mode is enabled when P/S is set to low. Direct Parallel Mode - Outputs are changed by the Control Voltage Inputs directly. The LE (Latch Enable) must be at a logic high to control in this manner. Latched Parallel Mode - Outputs are selected using the Control Voltage Inputs and set while the LE is in the Low state. This will not change state while LE is Low. Once all Control Voltage Inputs are at the desired states the LE is pulsed. See timing diagram above for reference. Timing Diagram (Latched Parallel Mode) HMC677LP5 / 677LP5E v05.0810 6-Bit SERIAL/PARALLEL SWITCH DRIVER/CONTROLLER Parameter Typ. Min. serial period, t SCK 100 ns Control set-up time, t CS 20 ns Control hold-time, t CH 20 ns LE setup-time, t LN 10 ns Min. LE pulse width, t LEW 10 ns Min LE pulse spacing, t LES 630 ns Serial clock hold-time from LE, t CKN 10 ns Hold Time, t PH. 0 ns Latch Enable Minimum Width, t LEN 10 ns Setup Time, t PS 2 ns |
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