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12

HMC708LP5 / 708LP5E

v03.0409

0.5 dB LSB 6-BIT DIGITAL

VARIABLE GAIN AMPLIFIER, 1700 - 2200 MHz

PUP Truth Table

parameter

typ.

min. serial period, t

sCK

100 ns

Control set-up time, t

Cs

20 ns

Control hold-time, t

CH

20 ns

le setup-time, t

ln

10 ns

min. le pulse width, t

leW

10 ns

min le pulse spacing, t

les

630 ns

serial clock hold-time from le, t

CKn

10 ns

Hold time, t

pH.

0 ns

latch enable minimum Width, t

len

10 ns

setup time, t

ps

2 ns

Truth Table

Note: the parallel mode is enabled when p/s is set to low.

Direct Parallel Mode - the attenuation state is changed by the Control Voltage inputs directly. the le (latch enable)

must be at a logic high to control the attenuator in this manner.

Latched Parallel Mode - the attenuation state is selected using the Control Voltage inputs and set while the le is in

the low state. the attenuator will not change state while le is low. Once all Control Voltage inputs are at the desired

states the le is pulsed. see timing diagram above for reference.

Power-Up States

le

pUp1

pUp2

gain relative to maximum

gain

0

0

0

-31.5

0

1

0

-24

0

0

1

-16

0

1

1

insertion loss

1

X

X

0 to -31.5 db

note: the logic state of d0 - d5 determines the

power-up state per truth table shown below when le

is high at power-up.

Control Voltage input

gain

relative to

maximum

gain

d5

d4

d3

d2

d1

d0

High

High

High

High

High

High

0 db

High

High

High

High

High

low

-0.5 db

High

High

High

High

low

High

-1 db

High

High

High

low

High

High

-2 db

High

High

low

High

High

High

-4 db

High

low

High

High

High

High

-8 db

low

High

High

High

High

High

-16 db

low

low

low

low

low

low

-31.5 db

any combination of the above states will provide a reduction in

gain approximately equal to the sum of the bits selected.

if le is set to logic lOW at power-up, the logic state of

pUp1 and pUp2 determines the power-up state of the

part per pUp truth table. if the le is set to logic HigH

at power-up, the logic state of d0-d5 determines the

power-up state of the part per truth table. the dVga

latches in the desired power-up state approximately

200 ms after power-up.

Power-On Sequence

the ideal power-up sequence is: gnd, Vdd, digital

inputs, rf inputs. the relative order of the digital

inputs are not important as long as they are powered

after Vdd / gnd

Control Voltage Table

state

Vdd = +3V

Vdd = +5V

low

0 to 0.5V @ <1 µa

0 to 0.8V @ <1 µa

High

2 to 3V @ <1 µa

2 to 5V @ <1 µa