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Phone: 978-250-3343

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12

Absolute Maximum Ratings

17.5 dBm (T = +85 °C)

Digital Inputs (Reset, Shift Clock,

Latch Enable & Serial Input)

-0.5 to Vdd +0.5V

Bias Voltage (Vdd)

5.6V

Collector Bias Voltage (Vcc)

5.5V

Channel Temperature

175 °C

Continuous Pdiss (T = 85 °C)

1.2 W

75.6 °C/W

Storage Temperature

-65 to +150 °C

Operating Temperature

-40 to +85 °C

[1] The maximum RF input power increases by the same amount

the gain is reduced. The maximum input power at any state is no

more than 28 dBm.

[2] This value does not include the RF power dissipation in the

attenuator. The loss in the attenuator depends on the state of

the attenuator. The loss in the attenuator should be included to

determine the total power dissipation in the part.

[3] This value does not include the RF power dissipation in the

attenuator. The thermal resistance at different states of the

attenuator can be determined based on note [2]

ELECTROSTATIC SENSITIVE DEVICE

OBSERVE HANDLING PRECAUTIONS

Bias Voltage

PUP Truth Table

LE

PUP1

PUP2

Gain Relative to Maximum

Gain

0

0

0

-31.5

0

1

0

-24

0

0

1

-16

0

1

1

Insertion Loss

1

X

X

0 to -31.5 dB

Note: The logic state of D0 - D5 determines the

power-up state per truth table shown below when LE

is high at power-up.

Power-Up States

Vdd (V)

Idd (Typ.) (mA)

+5.0

2

Vs (V)

Is (mA)

+5.0

150

Control Voltage Input

Gain

Relative to

Maximum

Gain

D5

D4

D3

D2

D1

D0

High

High

High

High

High

High

0 dB

High

High

High

High

High

Low

-0.5 dB

High

High

High

High

Low

High

-1 dB

High

High

High

Low

High

High

-2 dB

High

High

Low

High

High

High

-4 dB

High

Low

High

High

High

High

-8 dB

Low

High

High

High

High

High

-16 dB

Low

Low

Low

Low

Low

Low

-31.5 dB

Any combination of the above states will provide a reduction in

gain approximately equal to the sum of the bits selected.

Truth Table

If LE is set to logic LOW at power-up, the logic state of

PUP1 and PUP2 determines the power-up state of the

part per PUP truth table. If the LE is set to logic HIGH

at power-up, the logic state of D0-D5 determines the

power-up state of the part per truth table. The DVGA

latches in the desired power-up state approximately

200 ms after power-up.

Power-On Sequence

The ideal power-up sequence is: GND, Vdd, digital

inputs, RF inputs. The relative order of the digital

inputs are not important as long as they are powered

after Vdd / GND

HMC742LP5E

v05.0610

0.5 dB LSB GaAs MMIC 6-BIT DIGITAL

VARIABLE GAIN AMPLIFIER, 70 MHz - 4 GHz

Control Voltage Table

State

Vdd = +3V

Vdd = +5V

Low

0 to 0.5V @ <1 µA

0 to 0.8V @ <1 µA

High

2 to 3V @ <1 µA

2 to 5V @ <1 µA