G3

G2

A1

A0

R/nW

ACK

Start

G1

G0

A2

S7

S6

S2

S1

S5

S4

S3

S0

ACK

D7

D6

D2

D1

D5

D4

D3

D0

ACK

Stop

Slave Address + R/nW

Sub Address

Data

DRV201

www.ti.com

SLVSB25

– AUGUST 2011

VCM DRIVER OUTPUT STAGE OPERATION

Current in the VCM can be controlled with a linear or PWM mode output stage. Output stage is enabled in

ACTIVE mode which can be controlled through VCM_CURRENT control register and the output stage mode is

selected from MODE register bit PWM/LIN.

In linear mode the output PMOS is configured to a high side current source and current can be controlled from a

VCM_CURRENT registers.

In PWM control the VCM is driven with a half bridge driver. With PWM control the VCM current is increased by

mode through the sense resistor and low side NMOS. Current in the VCM is sensed with a 1-

Ω sense resistor

which is connected into an error amplifier input where the other input is controlled by the 10-bit DAC output.

PWM mode switching frequency can be selected from 0.5 MHz up to 4 MHz through a CONTROL register. PWM

or linear mode can be selected with the PWM/LIN bit in the MODE register.

RINGING COMPENSATION

spring which causes a dampened ringing in the lens position when current is changed. This mechanical ringing is

compensated internally by generating an optimized ramp when ever the current value in the VCM_CURRENT

register is changed. This enables a fast auto focus algorithm and pleasant user experience.

Ringing compensation is dependent on the VCM resonance frequency and this can be controlled via

VCM_FREQ register from 50 Hz up 152 Hz with 0.4-Hz steps. Ringing compensation is designed in a way that it

can tolerate

±20% frequency variation in the VCM resonance frequency so only statistical data from the VCM is

needed in production.

I

Start

– Start condition

G(3:0)

– Group ID: Address fixed at '0001'

A(2:0)

– Device Address: Address fixed at '110'

R/nW

– Read/not Write select bit

ACK

– Acknowledge

S(7:0)

– Subaddress: Defined per register map

D(7:0)

– Data: Data to be loaded into the device

Stop

– Stop condition

using a two-wire bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is

sourced from the controller in all cases where the serial data line is bi-directional for data communication

between the controller and the slave terminals. Each device has an open drain output to transmit data on the

serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high

during data transmission.

Copyright

© 2011, Texas Instruments Incorporated

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