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ADS5263 Datasheet(PDF) 1 Page - Texas Instruments |
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ADS5263 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 75 page ADS5263 www.ti.com SLAS760B – MAY 2011 – REVISED OCTOBER 2011 Quad Channel 16-Bit, 100-MSPS High-SNR ADC Check for Samples: ADS5263 1 FEATURES APPLICATIONS • Maximum Sample Rate: 100 MSPS • Medical Imaging – MRI • Programmable Device Resolution • Spectroscopy – Quad-Channel, 16-Bit, High-SNR Mode • CCD Imaging – Quad-Channel, 14-Bit, Low-Power Mode DESCRIPTION • 16-Bit High-SNR Mode Using CMOS process technology and innovative – 1.4 W Total Power at 100 MSPS circuit techniques, the ADS5263 is designed to – 355 mW / Channel operate at low power and give very high SNR performance with a 4-Vpp full-scale input. Using a – 4 Vpp Full-scale Input low-noise 16-bit front-end stage followed by a 14-bit – 85-dBFS SNR at fin = 3 MHz, 100 MSPS ADC, the device gives 85-dBFS SNR up to 10 MHz • 14-Bit Low-Power Mode and better than 80-dBFS SNR up to 30 MHz. – 785 mW Total Power at 100 MSPS The device also has a 14-bit low power mode, where – 195 mW/Channel it operates as a quad-channel 14-bit ADC. The 16-bit front-end stage is powered down and the part – 2-Vpp Full-Scale Input consumes almost half the power, compared to the – 74-dBFS SNR at fin = 10 MHz 16-bit mode. The 14-bit mode supports a 2-Vpp – Integrated Clamp (for interfacing to CCD full-scale input signal, with typical 74-dBFS SNR. The sensors) ADS5263 can be dynamically switched between the two resolution modes. This allows systems to use the • Low-Frequency Noise Suppression same part in a high-resolution, high-power mode or a • Digital Processing Block low-resolution, low-power mode. – Programmable FIR Decimation Filters The ADS5263 has a digital processing block that – Programmable Digital Gain: 0 dB to 12 dB integrates several commonly used digital functions, – 2- or 4-Channel Averaging such as digital gain (up to 12 dB). It includes a digital filter module that has built-in decimation filters (with • Programmable Mapping Between ADC Input low-pass, high-pass and band-pass characteristics). Channels and LVDS Output Pins —Eases The decimation rate is also programmable (by 2, by Board Design 4, or by 8). This makes it very useful for narrow-band • Variety of Test Patterns to Verify Data Capture applications, where the filters can be used to improve by FPGA/Receiver SNR and knock-off harmonics, while at the same time reducing the output data rate. • Serialized LVDS Outputs • Internal and External References The device includes an averaging mode where two channels (or even four channels) can be averaged to • 3.3-V Analog Supply improve SNR. A very unique feature is the • 1.8-V Digital Supply programmable mapper module that allows flexible • Recovers From 6-dB Overload Within 1 Clock mapping between the input channels and the LVDS Cycle output pins. This helps to greatly reduce the complexity of LVDS output routing and can potentially • Package: result in cheaper system boards by reducing the – 9-mm × 9-mm 64-Pin QFN number of PCB layers. – Non-magnetic package option for MRI systems • CMOS Technology 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2011, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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