LA72680M

PS No.7955-20/21

I

(1) DATA TRANSFER MANUAL

SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale of

Bit),and save the order. The 9th bit takes ACK (ACKnowledge) period, during SCL terminal takes “H”, this IC pull

down the SDA terminal. After transferred the necessary data, two terminals lead to set up and of data transfer stop

As a part of transfer data write down to internal memory (V latch system), internal control

doesn’t change just after the transfer.

*1 Defined by SCL rise down SDA during ‘H’ period.

*2 Defined by SCL rise up SDA during ‘H’ period.

(2) TRANSFER DATA FORMAT

After transfer start condition, transfers slave address(1110100*) to SDA terminal, next, sub address(0000****),

Data works with all of the bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be

canceled only the data of group.

*3 There are 1 to 5 groups.

*4 Pointed date by sub address becomes group No. of next control data.

Fig.1 DATA STRUCTURE “WRITE” mode

START

Condition

Slave

Address

R/W

L

*5

ACK Sub Address(n) ACK Control data(n) ACK

control data(n+1)

ACK ……

STOP condition

*5 It is called R/W bit.

data-1 means data for group-1, data-2 means data for group-2.

(3) INITIALIZE

This IC is initialized for circuit protection.

The initialization period is decided Pin 16 capacity value by internal impedance 15kΩ, and shown with

t = -CR

×Ln(0.2). Data cannot be accepted for this period.

t = 530ms at C = 22

µF, In this case, Please transmit data in consideration of the uneven after about 700ms.