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LA73026AV Datasheet(PDF) 9 Page - Sanyo Semicon Device

Part No. LA73026AV
Description  Double Scart Interface IC
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Maker  SANYO [Sanyo Semicon Device]
Homepage  http://www.ssdc-jp.com/eng/
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LA73026AV
No.A0239-9/13
Serial Control Specification
Slave address
MSB
LSB
1
0
0
1
0
1
0
0
Slave receiver
Data format
S
Slave address (8bit)
A
Sub address (8bit)
A
Data address (8bit)
A
P
Start condition
Acknowledge
Stop condition
Sub address and data byte table
Data byte (Underline is initial setting.)
MSB
LSB
Sub address
Hexadecimal
D8
D7
D6
D5
D4
D3
D2
D1
01
(0000 0001)
SW1
00: C
01: B
10: A
11: A
SW2
00: D
01: C
10: B
11: A
SW3
00: C
01: B
10: A
11: *
FSSOUT
00: HIGH
01: HIGH
10: MID
11: LOW
02
(0000 0010)
EXT
CTL1
0: L
1: H
EXT
CTL2
0: L
1: H
AMP GAIN
VPS OUT
0: 0dB
1: 6dB
AUDIO AMP GAIN1
(DEC OUT)
000: 0dB
001: 2dB
010: 4dB
011: 6dB
100:12dB
AUDIO AMP GAIN2
(EXT OUT)
00: 0dB
01: 2dB
10: 4dB
11: 6dB
03
(0000 0011)
MUTE1
VSW1 OUT
0: through
1: MUTE
MUTE2
VSW2 OUT
0: through
1: MUTE
MUTE3
VSW3 OUT
0: through
1: MUTE
MUTE4
ASW1 OUT
0: through
1: MUTE
MUTE5
ASW2 OUT
0: through
1: MUTE
MUTE6
ASW3 OUT
0: through
1: MUTE
EXT
CTL3
0: L
1: H
EXT
CTL4
0: L
1: H
Data transfer
I
2C-BUS control system is adopted in SW IC and SW IC is controlled by SCL (Serial Clock) and SDA (Serial Data) At
first, please set up the START condition
*1 by these two terminals (SCL and SDA). And next, please input the 8bits data
which should be synchronized with SCL into SDA terminal. Still more, please give priority to high rank bit at data
transfer order (MSB
→ LSB). The 9th bit is called as ACK (Acknowledge), SW IC sends [0] to the SDA terminal
during SCL [1] period. So, please open the port of micro-processor during this period. LA73026AV adopt
auto-increment, so you input only first sub-address data (called as Group) and you can transfer data in order. As thus
the Data transfer Stop condition
*2 is finished.
*1 SDA rise up during SCI is [1]
*2 SDA fall down during SCL is [1]




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