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LE25FW806 Datasheet(PDF) 3 Page - Sanyo Semicon Device |
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LE25FW806 Datasheet(HTML) 3 Page - Sanyo Semicon Device |
3 / 22 page LE25FW806 No.A0838-3/22 Figure 2 Block Diagram Table 1 Pin Description Symbol Pin Name Description SCK Serial clock This pin controls the data input/output timing. The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is output synchronized to the falling edge of the serial clock. SI Serial data input The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the serial clock. SO Serial data output The data stored inside the device is output from this pin synchronized to the falling edge of the serial clock. CS Chip select The device becomes active when the logic level of this pin is low; it is deselected and placed in standby status when the logic level of the pin is high. WP Write protect The status register write protect (SRWP) takes effect when the logic level of this pin is low. HOLD Hold Serial communication is suspended when the logic level of this pin is low. VDD Power supply This pin supplies the 2.70 to 3.60V supply voltage. VSS Ground This pin supplies the 0V supply voltage. 8M Bit Flash EEPROM Cell Array Y-DECODER I/O BUFFERS & DATA LATCHES CS SCK SI HOLD WP SO X- DECODER ADDRESS BUFFERS & LATCHES SERIAL INTERFACE CONTROL LOGIC |
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