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LE25LB643 Datasheet(PDF) 10 Page - Sanyo Semicon Device |
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LE25LB643 Datasheet(HTML) 10 Page - Sanyo Semicon Device |
10 / 14 page LE25LB643 No.NA1342-10/14 BP0, BP1 (bits2, 3) Block Protect Settings Block protect BP0 and BP1 are status register bits that can be rewritten, and the memory space to be protected can be set depending on these bits. For the setting conditions, refer to “Table 3 Protect Level Setting Conditions.” Table 3 Protect Level Setting Conditions Status Register Bits Protection Block (Level) BP1 BP0 Protected Area 0 (Whole area unprotected) 0 0 None 1 (Upper 1/4 area protected) 0 1 1800h to 1FFFh 2 (Upper 1/2 area protected) 1 0 1000h to 1FFFh 3 (Whole area protected) 1 1 0000h to 1FFFh SRWP (bit7) Status Register Write Protect Settings Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten. When SRWP is “1” and the logic level of the WP pin is low, the status register write command is ignored, and status registers BP0, BP1, BP2, and SRWP are protected. When the logic level of the WP pin is high, the status registers are not protected regardless of the SRWP state. The SRWP setting conditions are shown in “Table 4 SRWP Setting Conditions.” Table 4 SRWP Setting Conditions WP Pin SRWP Mode Status Register Protected Area Unprotected Area 1 0 0 0 1 1 Software protected (SPM) Unprotected Protected Unprotected 0 1 Hardware protected (HPM) Protected Protected Unprotected Bit4, bit5, and bit6 are reserved bits, and have no significance. 3. Write Enable (WREN) Before performing any of the operations listed below, the device must be placed in the write enable state. Operation is the same as for setting status register WEN to “1”, and the state is enabled by inputting the write enable command. “Figure 7 Write Enable” shows the timing waveforms when the write enable operation is performed. The write enable command consists only of the first bus cycle, and it is initiated by inputting (06h). • Write (WRITE) • Status register write (WRSR) 4. Write Disable (WRDI) The write disable command sets status register WEN to “0” to prohibit unintentional writing. “Figure 8 Write Disable” shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is initiated by inputting (04h). The write disable state (WEN “0”) is exited by setting WEN to “1” using the write enable command (06h). Figure 7 Write Enable Figure 8 Write Disable CS SCK SI SO 8CLK 06h High Impedance Mode3 Mode0 01 2 3 4 5 6 7 (00000110) CS SCK SI SO 8CLK 04h High Impedance Mode3 Mode0 01 2 3 4 5 6 7 (00000100) |
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