LV5050NV

PS No.A1159-7/7

SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using

products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition

ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.

products described or contained herein.

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semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or

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limited to protective circuits and error prevention circuits for safe design, redundant design, and structural

design.

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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed

for volume production.

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Continued from preceding page.

Pin No.

Pin name

Description

14

UV_DELAY

UVP DELAY pin

By connecting a capacitor between this pin and SGND, the time until the IC latches off after detecting the UVP state can be

set. Also, after channel 1 terminated the soft-start function, when the output voltage becomes -80% or less for the setup

voltage, an external capacitor is charged by the constant current source of 8.6

µA in the IC.

When this terminal voltage becomes 2.4V or more, the IC is latched off.

If an external capacitor is not connected, the IC is instantly latched off after detecting the UVP state.

Also, when this pin is shorted to GND, the UV_DELAY function is not operated.

15

FB

Feed back input pin. The minus terminal (-) of the trans conductance amplifier is connected.

The voltage generated when the output voltage was divided by a resistor is input into this pin.

The converter operates so that this pin becomes an internal reference voltage (VREF=0.836V).

Also, this pin is monitored by the comparators UVP and OVP.

When the voltage of this pin becomes less than 87% of the set voltage, the PGOOD pin is low level.

A timer of the UV_DELAY function operates. Also, when the voltage of this pin becomes more than 117% of the set voltage,

the IC latches off.

16

COMP

The pin to connect a capacitor and a resistor for phase compensation.

The output of an internal transformer conductance amplifier is connected.

Connect an external phase compensation circuit between this pin and SGND.

17

SGND

The system ground of the IC. The reference voltage is generated based on this pin.

This pin is connected to the power supply system ground.

18

VDD

Power supply pin for the gate drive of an external lower-side MOS-FET.

This pin is connected to the VLIN5 pin through a filter.

19

LDRV

The gate drive pin of an external lower-side MOS-FET.

This pin has the signal input part for prevention of short-through of both the upper and lower MOS-FETs.

When the voltage of this pin becomes less than 1V, the HDRV pin is turned on.

20

PGND

Power ground pin. This pin becomes the return current path of the LDRV pin.

This catalog provides information as of December, 2008. Specifications and information herein are subject

to change without notice.