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HI-3588PQT Datasheet(PDF) 9 Page - Holt Integrated Circuits

Part # HI-3588PQT
Description  Receiver with SPI Interface
Download  11 Pages
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Manufacturer  HOLTIC [Holt Integrated Circuits]
Direct Link  http://www.holtic.com
Logo HOLTIC - Holt Integrated Circuits

HI-3588PQT Datasheet(HTML) 9 Page - Holt Integrated Circuits

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AC ELECTRICAL CHARACTERISTICS
HI-3588
ORDERING INFORMATION
HI - 3588 xx x x
PACKAGE
DESCRIPTION
44 PIN PLASTIC CHIP-SCALE, QFN (44PCS)
PART
NUMBER
PC
44 PIN PLASTIC QUAD FLAT PACK, PQFP (44PTQS)
PQ
LEAD
FINISH
PART
NUMBER
100% Matte Tin (Pb-free, RoHS compliant)
F
Tin / Lead (Sn / Pb) Solder
Blank
TEMPERATURE
RANGE
BURN
IN
-40°C TO +85°C
No
-55°C TO +125°C
No
T
PART
NUMBER
T
I
FLOW
I
The HI-3588PCI and HI-3588PCT use a 44-pin plastic
chip-scale package. This package has a metal heat sink
pad on its bottom surface that is electrically connected to
the die. For the HI-3588, the primary advantage of this
package is its small size; heat sinking provides little benefit
because HI-3588 dissipation is low. If connected, the heat
bottom sink pad should be connected to VDD.
Do not connect heat sink pad to GND.
HEAT SINK - CHIP-SCALE PACKAGE ONLY
LIMITS
PARAMETER
SYMBOL
UNITS
MIN
TYP
MAX
SPI INTERFACE TIMING
RECEIVER TIMING
SCK clock period
active after last SCK rising edge
t
20
ns
setup time to first SCK rising edge
t
10
ns
hold time after last SCK falling edge
t
40
ns
inactive between SPI instructions
t
Delay - Last bit of received ARINC word to RFLAG(Full or Empty) - Hi Speed
t
16
µs
Received data available to SPI interface. RFLAG to
active
SPI receiver read or clear FIFO instruction to RFLAG
t
t
200
ns
35
ns
SPI SI Data set-up time to SCK rising edge
t
30
ns
SPI SI Data hold time after SCK rising edge
t
30
ns
SCK rise time
t
10
ns
SCK fall ime
t
10
ns
SCK pulse width high
t
90
ns
SCK pulse width low
t
80
ns
SO valid after SCK falling edge
t
130
ns
SO high-impedance after SCK falling edge
t
100
ns
Delay - Last bit of received ARINC word to RFLAG(Full or Empty) - Lo Speed
t
126
µs
t0
ns
155
ns
CYC
CPH
DS
DH
SCKR
SCKF
SCKH
SCKL
DV
CHZ
RFLG
RXR
CS
CS
CS
CS
CS
CHH
CES
CEH
RFLG
SPIF
VDD = 3.3V or 5.0V, GND = 0V, TA = Operating Temperature Range and fclk=1MHz 0.1% with 60/40 duty cycle
+
HOLT INTEGRATED CIRCUITS
9


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