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HI-3717PCM Datasheet(PDF) 11 Page - Holt Integrated Circuits |
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HI-3717PCM Datasheet(HTML) 11 Page - Holt Integrated Circuits |
11 / 23 page 0 MSB 1 0 0 1 1 1 0 1 0 1 +5V Harvard Bi-Phase -5V +10V Bi-Polar Return to Zero -10V FIGURE 6. ARINC 717 HBP & BPRZ Differential Input Signal Format FUNCTIONAL DESCRIPTION (cont.) Data 1 LSB The first word stored in the Receive FIFO is available when RXFSTAT<2>, RFEMPTY, is reset to “0”, which is 12-bit periods (one word time) after INSYNC is set to “1”. The HI-3717 remains in sync as long as the proper sync sequence is maintained. INSYNC is reset to “0” when the next expected subframe sync mark is not present. The HI-3717 will initiate a new synchronization process at the next valid SYNC1 mark. Once the part falls out of sync, the whole previous subframe should be discarded. 2. Test Mode In this mode the HI-3717 searches for any two subframe sync marks in the correct sequential order and the exact starting time for the sync mark. INSYNC is set to “1” when the third valid sync mark is detected. The part must continue to detect each sync mark in the correct order and with the correct starting time to stay in sync. This method reduces the time required to obtain sync to about 2 seconds typical and a worst case of 3 seconds. 3. No Sync Detect Mode In this mode, the INSYNC is set to “1” and all data is stored in the Receive FIFO. Without sync detection, the Receive FIFO just records the sequential bits, not words, from the bus. It is up to the user to detect the sync marks and determine the word boundaries in this mode. In both the Flight Recorder Mode and the Test Mode, the HI-3717 uses a proprietary sync tracking and detection method which allows multiple random false sync marks in the user data without increasing the sync time. Digital Loopback Normal HI-3717 operation is with CTRL1<0> set to “0”. Setting it to “1” places the part in digital loopback mode. In this mode the analog line receivers are disconnected from the data samplers and both output line drivers are placed in a high impedance state. The output encoders are connected to input sampler / decoder. The part may be verified by selecting the desired receive decode format with RSEL pin or CTRL1<0>, writing the transmit FIFO and reading the receive FIFO. All status pins and registers reflect the status of the loopback operation. FIFO Status Pin Assignment Register, FSPIN This register assigns the function of the external RFIFO and TFIFO pins. The RFIFO pin reflects the state of one of the three Receive FIFO status flags (RFFULL, RFHALF and RFEMPTY) in the Receive FIFO Status Register, RXFSTAT. The TFIFO pin reflects the state of one of two Transmit FIFO status flags (TFULL or TFHALF) in the TFXSTAT register. Refer to the FSPIN Register Description in Table 7 for register assignment details. Word Count Utility Register, WRDCNT The MATCH pin goes high when the HI-3717 is in the INSYNC condition and the word count and subframe count matches the value programmed in the Word Count Utility Register. Note: The INSYNC pin is set to “1” when the second consecutive SYNC1 mark of the proper sync sequence is received. The Word Count Utility Register and Match pin function can be used for the standard ARINC 717 data rates and all of the expanded data rates, except 8192 wps. ARINC 717 RECEIVER The input data stream for ARINC 717 can be one of two formats. The main ARINC 717 bus to a Digital Flight Data Recorder (DFDR) uses Harvard Bi-phase (HBP) encoding and the auxiliary output bus to an Aircraft Integrated Data System (AIDS) uses Bi-Polar Return to Zero (BPRZ) encoding as shown in Figure 6. The HI-3717 has an independent ARINC 717 receive channel with a selectable on-chip HBP analog line receiver for connection to the main incoming ARINC 717 data bus or a BPRZ analog line receiver for connection to an auxiliary data bus. The ARINC 717 specification requires the following detection levels for the HBP inputs: STATE DIFFERENTIAL VOLTAGE HI +2 Volts to +8 Volts NULL NA LO -2 Volts to -8 Volts HI-3717 HOLT INTEGRATED CIRCUITS 11 |
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