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HI-3717PCTF Datasheet(PDF) 5 Page - Holt Integrated Circuits |
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HI-3717PCTF Datasheet(HTML) 5 Page - Holt Integrated Circuits |
5 / 23 page FIGURE 3. Single-Byte Read From a Register CS SO SI SCK MSB LSB 0 1 2 3 4 5 6 7 High Z High Z 0 1 2 3 4 5 6 7 MSB LSB MSB LSB Data Byte Op-Code Byte Host may continue to assert CS here to read sequential byte(s) when allowed by the instruction. Each byte needs 8 SCK clocks. FIGURE 4. 2-Byte SPI Write Example CS SO SI SCK SPI Mode 0 MSB LSB 0 1 2 3 4 5 6 7 High Z 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 MSB LSB MSB LSB Data Byte 0 Data Byte 1 Op-Code Byte Host may continue to assert CS here to write sequential byte(s) when allowed by the SPI instruction. Each byte needs 8 SCK clocks. Figure 3 and Figure 4 show read and write timing as it appears for a single-byte and dual-byte register operation. The instruction op code is immediately followed by a data byte comprising the 8-bit data word read or written. For a register read or write, CS is negated after the data byte is transferred. Table 2 summarizes the HI-3717 SPI instruction set. Note: SPI Instruction op-codes not shown in Table 2 are “reserved” and must not be used. Further, these op-codes will not provide meaningful data in response to a read instruction. Two instruction bytes cannot be “chained”; CS must be negated after each instruction, and then reasserted for the following Read or Write instruction. HOLT INTEGRATED CIRCUITS 5 HI-3717 |
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