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HI-5002CRI Datasheet(PDF) 6 Page - Holt Integrated Circuits |
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HI-5002CRI Datasheet(HTML) 6 Page - Holt Integrated Circuits |
6 / 13 page DC ELECTRICAL CHARACTERISTICS (cont.) V = 5V 5%, Operating temperature range. Positive currents flow into the IC. DD ± LIMITS PARAMETER CONDITIONS UNIT SYMBOL MIN TYP MAX Input leakage current, unpowered node I , I V = 0 V 200 + 200 μA CANH CANL DD Short-circuit steady-state output current I V = +58V, V open -20 20 mA V = -58V, V openV -200 100 mA V = +58V, V open 100 200 mA V = -58V, V open (See Fig. 6) -20 20 mA Differential receiver threshold voltage V 12V<V ,V <+12V 500 700 900 mV Differential hysteresis voltage V 12V<V ,V <+12V 50 120 200 mV Differential hysteresis voltage in Standby mode V 12V<V ,V <+12V 500 1150 mV V V= V = 5V Differential input resistance R V = V 12V<V ,V <+12V 2 50 75 k Common mode input resistance R V = V 12V<V ,V <+12V 1 30 45 k RV = V 3 + 3 % OS(ss) CANH CANL CANH CANL CANL CANH CANL CANH Th(Rx)(diff) CANH CANL Hys(Rx)(diff) CANH CANL Hys(Stb)(diff) CANH CANL IO CANH CANL IN(DIFF) TXD DD CANH CANL IN(CM) TXD DD CANH CANL IN(CM)(m) CANH CANL RECEIVER − − − − −5 Ω −5 Ω Deviation between common mode input resistance between CANH and CANL − HOLT INTEGRATED CIRCUITS 6 HI-5000, HI-5001, HI-5002 AC ELECTRICAL CHARACTERISTICS V = 5V 5%, Operating temperature range. Positive currents flow into the IC. DD ± NOTES: 1. All currents into the device pins are positive; all currents out of the device pins are negative. 2. All typicals are given for V = 5V, T = 25°C. 3. Guaranteed by design but not tested. DD A LIMITS PARAMETER CONDITIONS UNIT SYMBOL MIN TYP MAX Delay TXD to bus active t 40 90 ns dr(TXD) Bit time t 1 25 μs Bit rate f 40 1000 kHz Common mode input capacitance C V = V , 1Mbit/s data rate 20 pF Differential input capacitance C V = V , 1Mbit/s data rate 10 pF Delay TXD to bus inactive t See Timing Diagrans 40 90 ns Delay bus active to RXD t 30 70 ns Delay bus inactive to RXD t 70 150 ns Propagation delay TXD to RXD (recessive to dominant) t 70 160 ns Propagation delay TXD to RXD (dominant to recessive) t 110 240 ns TXD permanent dominant time-out t V = 0 V 0.3 2 6 ms TXD permanent dominant timer reset time t Rising edge on TXD while in permanent dominant state 1 μs Dominant time required on bus for standby receiver t 0.5 3 5 μs detection Bit Bit IN(CM) TXD DD DIFF(CM) TXD DD df(TXD) df(RXD) dr(RXD) Prop1 Prop2 dom TXD Rdom 3 3 wake |
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