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TFA9881 Datasheet(PDF) 6 Page - NXP Semiconductors |
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TFA9881 Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 32 page TFA9881 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 1 April 2011 6 of 32 NXP Semiconductors TFA9881 3.4 W PDM input class-D audio amplifier 8.3 Power up/down sequence The TFA9881 power-up/power-down sequence is shown in Figure 6. External power supplies VDDP and VDDD should be within their operating limits before the TFA9881 switches to Operating mode. The TFA9881 should be switched to Power-down mode before the power supplies are disconnected or turned off. [1] RL = load resistance; LL = load inductance. [2] Inversely proportional to fclk. Fig 5. Digital stereo PDM selection Table 5. Left/right selection LRSEL pin state Description LOW left content amplified HIGH right content amplified 010aaa702 CLK DATA LEFT RIGHT Fig 6. Power-up/power-down sequence VDDP, VDDD CLK 128·fs or 64·fs clock signal DATA OUTA, OUTB td(on) Power-down Operating Mute Operating Mute Power-down td(on) Operating td(off) Power-down switching PDM 32 times 0x66 floating 0x66 ....... PDM switching 32 times 0xAC 96 times 0xAC 128 × 0xAC floating 0xAC ....... PDM switching 010aaa710 Table 6. Power-up/power-down timing All parameters are guaranteed for VTEST =VDDP = 3.6 V; VDDD = 1.8 V; RL =4 Ω[1]; LL =20 μH[1]; fi = 1 kHz; fclk = 6.144 MHz; Tamb = 25 °C; default settings, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit td(on) turn-on delay time [2] -- 2 ms td(off) turn-off delay time [2] -- 5 μs |
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